EP80579 Datasheet, PDF (369/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
For each type of error detected in a given unit, there is a bit that corresponds to that
error in the unit_FERR, unit_NERR, SERRCMD_unit, SMICMD_unit, SCICMD_unit, and
MCERRCMD_unit registers. (Note that one and only one xCMD bit can be enabled per
error type.) The first occurrence of an error type will be indicated by the bit assertion
in the unit_FERR. If that error occurs again than the corresponding bit will be set in the
unit_NERR register. When a bit is asserted in either the unit_FERR or unit_NERR, and if
the corresponding enable bit is set in one of the named CMD registers, then an error
signal will be asserted, corresponding to the name of the CMD register: DO_SERR,
DO_SCI, DO_SMI, or DO_MCERR. The assertion of the DO_SERR signal also requires
that the SERR enable in the PCICMD register is set. The assertion of the DO_SERR
signal also causes the appropriate SERR signaled status bit to be set in the PCISTS
register.
Table 14-1. Pseudocode for EDMA Errors (Sheet 1 of 2)
Condition
Source
Action
The descriptor pointer
in next descriptor
address register is of
incorrect type or range
for EDMA channel 3.
The descriptor pointer
in next descriptor
address register is not
aligned to eight
double-word boundary
for EDMA channel 3.
The source address
does not comply with
the source type or
range for EDMA
channel 3.
The source address is
not aligned as specified
by the source address
bit for EDMA channel
3.
The destination
address does not
comply with the
destination type or
range for EDMA
channel 3.
Internal
DO_SERR and set PCISTS10[SSE] if (PCICMD10[SERRE]=1 AND
EDMA_EMASK[7]=0 AND SERRCMD_EDMA[7]=1 AND
R_EDGE{EDMA_FERR[31] OR EDMA_NERR[31]});
DO_SMI if EDMA_EMASK[7]=0 AND SMICMD_EDMA[7]=1 AND
R_EDGE{EDMA_FERR[31] OR EDMA_NERR[31]};
DO_SCI if EDMA_EMASK[7]=0 AND SCICMD_EDMA[7]=1 AND
R_EDGE{EDMA_FERR[31] OR EDMA_NERR[31]};
DO_MCERR if EDMA_EMASK[7]=0 AND MCERRCMD_EDMA[7]=1 AND
R_EDGE{EDMA_FERR[31] OR EDMA_NERR[31]};
Internal
DO_SERR and set PCISTS10[SSE] if (PCICMD10[SERRE]=1 AND
EDMA_EMASK[6]=0 AND SERRCMD_EDMA[6]=1 AND
R_EDGE{EDMA_FERR[30] OR EDMA_NERR[30]});
DO_SMI if EDMA_EMASK[6]=0 AND SMICMD_EDMA[6]=1 AND
R_EDGE{EDMA_FERR[30] OR EDMA_NERR[30]};
DO_SCI if EDMA_EMASK[6]=0 AND SCICMD_EDMA[6]=1 AND
R_EDGE{EDMA_FERR[30] OR EDMA_NERR[30]};
DO_MCERR if EDMA_EMASK[6]=0 AND MCERRCMD_EDMA[6]=1 AND
R_EDGE{EDMA_FERR[30] OR EDMA_NERR[30]};
Internal
DO_SERR and set PCISTS10[SSE] if (PCICMD10[SERRE]=1 AND
EDMA_EMASK[5]=0 AND SERRCMD_EDMA[5]=1 AND
R_EDGE{EDMA_FERR[29] OR EDMA_NERR[29]});
DO_SMI if EDMA_EMASK[5]=0 AND SMICMD_EDMA[5]=1 AND
R_EDGE{EDMA_FERR[29] OR EDMA_NERR[29]};
DO_SCI if EDMA_EMASK[5]=0 AND SCICMD_EDMA[5]=1 AND
R_EDGE{EDMA_FERR[29] OR EDMA_NERR[29]};
DO_MCERR if EDMA_EMASK[5]=0 AND MCERRCMD_EDMA[5]=1 AND
R_EDGE{EDMA_FERR[29] OR EDMA_NERR[29]};
Internal
DO_SERR and set PCISTS10[SSE] if (PCICMD10[SERRE]=1 AND
EDMA_EMASK[4]=0 AND SERRCMD_EDMA[4]=1 AND
R_EDGE{EDMA_FERR[28] OR EDMA_NERR[28]});
DO_SMI if EDMA_EMASK[4]=0 AND SMICMD_EDMA[4]=1 AND
R_EDGE{EDMA_FERR[28] OR EDMA_NERR[28]};
DO_SCI if EDMA_EMASK[4]=0 AND SCICMD_EDMA[4]=1 AND
R_EDGE{EDMA_FERR[28] OR EDMA_NERR[28]};
DO_MCERR if EDMA_EMASK[4]=0 AND MCERRCMD_EDMA[4]=1 AND
R_EDGE{EDMA_FERR[28] OR EDMA_NERR[28]};
Internal
DO_SERR and set PCISTS10[SSE] if (PCICMD10[SERRE]=1 AND
EDMA_EMASK[3]=0 AND SERRCMD_EDMA[3]=1 AND
R_EDGE{EDMA_FERR[27] OR EDMA_NERR[27]});
DO_SMI if EDMA_EMASK[3]=0 AND SMICMD_EDMA[3]=1 AND
R_EDGE{EDMA_FERR[27] OR EDMA_NERR[27]};
DO_SCI if EDMA_EMASK[3]=0 AND SCICMD_EDMA[3]=1 AND
R_EDGE{EDMA_FERR[27] OR EDMA_NERR[27]};
DO_MCERR if EDMA_EMASK[3]=0 AND MCERRCMD_EDMA[3]=1 AND
R_EDGE{EDMA_FERR[27] OR EDMA_NERR[27]};
Status
EDMA_FERR[31]
EDMA_FERR[30]
EDMA_NERR[29]
EDMA_FERR[28]
EDMA_FERR[27]
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
369