EP80579 Datasheet, PDF (1080/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.5.2
was not muxed). The time from STPCLK# inactive to the FERR# signal transitioning
back to the native function must be less than 120 ns.
5. At least 180 ns passes after deasserting STPCLK# and then starts using the FERR#
signal for an indication of a floating point error. The maximum time that may pass
is bounded such that it must have a chance to look at the FERR# signal before
reasserting STPCLK#. Based on current implementation, that maximum time would
be 240 ns (8 PCI clocks). Since the IA 32 core has 120 ns to revert to the proper
FERR# function, there are 60 ns of margin inherent in the timings.
The break event associated with this mechanism does not need to set any particular
status bit, since the pending interrupt will be serviced by the processor after returning
to the C0 state.
Transition Rules Among S0/Cx and Sx States
The following priority rules and assumptions apply among the various S0/Cx and
throttling states:
• Entry to any S0/Cx state is mutually exclusive with entry to S1, S3, S4 or S5 state.
This is because the processor can only perform one register access at a time and
Sleep states have higher priority than thermal throttling.
• ..When the SLP_EN bit is set (system going to a S1, S3, S4 or S5 sleep state), the
THTL_EN and FORCE_THTL bits can be internally treated as being disabled (no
throttling while going to sleep state).
• If the THTL_EN or FORCE_THTL bits are set, and a Level 2 read then occurs, the
system must immediately go and stay in a C2 state until a break event occurs. A
Level 2 read has higher priority than the software initiated throttling.
• After an exit from a C2 state (due to a Break event), and if the THTL_EN or
FORCE_THTL bits are still set, the system will continue to throttle STPCLK#. The
first transition on STPCLK# active can be delayed by up to one PROCHOT period
(1024 PCI clocks = 30.72 µs), depending on the time of the break event.
• The IMCH (or equivalent) must post Stop-Grant cycles in such a way that the
processor gets an indication of the end of the special cycle prior to CMI observing
the Stop-Grant cycle. This ensures that the STPCLK# signal stays active for a
sufficient period after the processor observes the response phase.
• If in the C1 state and the STPCLK# signal goes active, the processor will generate a
Stop-Grant cycle, and the system must go to the C2-like state. When STPCLK#
goes inactive, it must return to the C1 state.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1080
August 2009
Order Number: 320066-003US