EP80579 Datasheet, PDF (840/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-33. Offset 92h: PCS – Port Control and Status Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 92h
Offset End: 92h
Size: 16 bit
Default: 00h
Power Well: Core
Bit Range
15
14 : 13
12
11 : 08
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
Reserved
ORM
Reserved
Reserved
Reserved
P1P
P0P
Reserved
Reserved
P1E
POE
Reserved
Reserved
OOB Retry Mode (ORM): When cleared, the SATA
controller will not retry after an OOB failure. When set, the
SATA controller will continue to retry after an OOB failure
until successful (infinite retry)
Reserved
Reserved.
Reserved.
Port 1 Present (P1P): Same as P0P, except for port 1.
Port 0 Present (P0P): When set, the SATA controller has
detected the presence of a device on port 0. It may
change at any time. This bit is cleared when the port is
disabled via P0E. This bit is not cleared upon surprise
removal of a device.
Reserved.
Reserved.
Port 1 Enabled (P1E): When set, the port is enabled.
When cleared, the port is disabled. When enabled, the
port can transition between the on, partial, and slumber
states and can detect devices. When disabled, the port is
in the ‘off’ state and cannot detect any devices.This bit
takes precedence over P1CMD.SUD.
Port 0 Enabled (P0E):When set, the port is enabled.
When cleared, the port is disabled. When enabled, the
port can transition between the on, partial, and slumber
states and can detect devices. When disabled, the port is
in the ‘off’ state and cannot detect any devices.
This bit takes precedence over P0CMD.SUD.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RW
RO
RW
RWC
RO
RO
RO
RO
RO
RO
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
840
August 2009
Order Number: 320066-003US