EP80579 Datasheet, PDF (181/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 6-12. Power Wells Status for Supported ACPI States* (Sheet 2 of 2)
Power
Well
Supply Pin(s)
S0
S1
S3-cold
S4
S5
Suspend
RTC
VCC1P2_USBSUS
VCCSUS1
VCCSUS25
VCCPSUS
VCCGBEPSUS
VCC50_SUS
VCCPRTC
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
a. VTTDR, can optionally be powered off during S3, but typically is derived from and tracks DDR IO voltage,
VCC18, to avoid the complexity involved in timing the VTTDDR power up with the exit of S3.
b. VCCTMP18 and VCCAPE0PLL18 can optionally be powered off in S3 state. They are feed areas that consume
very little power and are grouped with VCC18, which must be on in S3, to avoid requiring an additional power
supply to support them.
6.3.2.1
Transitioning Between Power States
The EP80579 uses a cooperative power-down that is driven by software. To transition
from S0 into the S3 or S4 state under ACPI/BIOS/OS/device driver control, system
software is required to:
1. Suspend acceleration and security service application-level threads.
2. Place ASU and SSU devices into quiescent idle state, by completing all outstanding
work requests, saving internal state to memory, then disabling ASU/SSU interrupts.
3. Quiesce I/O interfaces by disabling Rx of new traffic, finalizing outstanding Tx
operations, disabling interrupts, and saving snap-shot of internal state to memory.
4. Save internal IMCH and IICH state to memory.
5. If transitioning to S4, move DRAM image to disk.
6. Drain all outstanding IMCH updates to DRAM.
7. Signal IICH to power-down the IA-32 core, the AIOC, the IMCH and the IICH. In
case of S3, the memory interface is placed into self-refresh mode. In S3/S4 state,
the GbE MAC, GPIO and LPC interfaces remain powered to process wake events.
An external wake event from GPIO, GbE MAC (received Wake-on-LAN packet) or PCI
Express* signals the IICH to initiate a complete reset sequence that transitions the
EP80579 back into the S0 state as follows:
1. All internal states outside of the IICH Resume Well are fully reset.
2. On resume from S3, BIOS does not reinitialize memory. Please refer to Section 6.2,
“BIOS Boot Flow (Initialization)” for details.
3. On resume from S3 or S4, all EP80579 device drivers (including ASU and SSU
drivers) are expected to restore internal device state from their memory resident
save area.
4. On resume from S3 or S4, resume acceleration and security service application-
level threads.
Note:
There is no support for wake from USB when in S3/S4/S5.
6.3.2.2
Power State Transition Timing Diagrams
For power state transition timing details, refer to Section 49.5.1.2, “Power Management
AC Characteristics”.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
181