EP80579 Datasheet, PDF (622/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.5.1.26 Offset D8h: DDQSCVDP1 - DQS DELAY CALIBRATION VICTIM PATTERN
1 Register
This register defines the first 32 bits of the 64 bit long “victim” data pattern.
Table 16-249.Offset D8h: DDQSCVDP1 - DQS Delay Calibration Victim Pattern 1 Register
Description: DDQSCVDP1: DQS Delay Cal Pattern
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: D8h
Offset End: DBh
Size: 32 bit
Default: 5b339c5dh
Power Well: Core
Bit Range
31 :00
Bit Acronym
VP1
Victim pattern 1
Bit Description
Sticky
Bit Reset
Value
5b339c5dh
Bit Access
RW
16.5.1.27 Offset DCh: DDQSCADP0 - DQS DELAY CALIBRATION AGGRESSOR
PATTERN 0 Register
This register defines the last 32 bits of the 64 bit long “aggressor” data pattern.
Table 16-250.Offset DCh: DDQSCADP0 - DQS Delay Calibration Aggressor Pattern 0
Register
Description: DDQSCADP0: DQS Delay Cal Pattern
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: DCh
Offset End: DFh
Size: 32 bit
Default: aaabffffh
Power Well: Core
Bit Range
31 :00
Bit Acronym
Bit Description
AP0
Aggressor pattern 0
Sticky
Bit Reset
Value
aaabffffh
Bit Access
RW
16.5.1.28 Offset E0h: DDQSCADP1 - DQS DELAY CALIBRATION AGGRESSOR
PATTERN 1 Register
This register defines the first 32 bits of the 64 bit long “aggressor” data pattern.
Intel^® EP80579 Integrated Processor Product Line Datasheet
622
August 2009
Order Number: 320066-003US