EP80579 Datasheet, PDF (1533/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.52 TSCTC – TCP Segmentation Context Transmitted Count Register
This register counts the number of TCP segmentation off load transmissions and
increments once the last portion of the TCP segmentation context payload is
segmented and loaded as a packet into the GbE hardware transmit buffer. Note that it
is not a measurement of the number of packets sent out (covered by other registers).
This register will only increment if transmits and TCP Segmentation off load are
enabled.
Table 37-129.TSCTC: TCP Segmentation Context Transmitted Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 40F8h
Offset End: 40FBh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 40F8h
Offset End: 40FBh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 40F8h
Offset End: 40FBh
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
TSCTC
Number of TCP Segmentation contexts transmitted count
Bit Reset
Value
0h
Bit Access
RC
37.6.6.53 TSCTFC – TCP Segmentation Context Transmit Fail Count Register
This register counts the number of TCP segmentation off load requests to the hardware
that failed to transmit all data in the TCP segmentation context payload (due to the
context specifying less data than the data descriptors reference). TCP Segmentation
requires the context's length specification to match the total length of the supplied data
descriptors, however. Therefore, this count should always be zero if TCP Segmentation
is properly used.
Table 37-130.TSCTFC: TCP Segmentation Context Transmit Fail Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 40FCh
Offset End: 40FFh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 40FCh
Offset End: 40FFh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 40FCh
Offset End: 40FFh
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
TSCTFC
Number of TCP Segmentation contexts where the device
failed to transmit the entire data payload
Bit Reset
Value
0h
Bit Access
RC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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