EP80579 Datasheet, PDF (117/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
3.3.2
.
Of the regions in Table 3-3, the “IA/ASU Shared (Coherent)” and “IA/ASU Shared
(AIOC-Direct)” regions are not managed by the IA O/S. The EP80579 software expects
that the BIOS carves this memory out of the memory map early in the boot process
and sets it aside for use by the Intel^® EP80579 Integrated Processor with Intel®
QuickAssist Technology software stack. As a result, the IA O/S does not allocate,
manage, page, etc. these regions of memory.
The regions in Table 3-3 fall into one of two categories with respect to IA cache
coherency: one that is coherent with IA caches for AIOC accesses and one that is not.
It is important to note that the coherent/non-coherent category of a region affects only
how the AIOC hardware handles a DRAM accesses. The category, in and of itself, does
not have any implications on how IA must always access the region.
The EP80579 expects that, in general, all agents in the system can access all memory,
consistent with their addressing capabilities, in the three regions that Table 3-3 lists.
Exceptions to this general rule may arise due to the size of the address space that an
agent supports or due to agent-specific aliasing of DRAM addresses onto other
structures. The following sections on the memory maps outline any agent-specific
exceptions. Finally, memory accesses that originate from the AIOC (or a device
attached to the AIOC) must honor the coherency requirements in Table 3-3 based on
the region they target. For consistency, software is expected to configure the EP80579
such that memory that the IA-32 core cannot access is not part of regions that are
expected to be coherent with IA caches.
Characteristics of Internal and External Memories
Table 3-4 defines the supported operations by memory type. The table uses the
following notation to indicate the behavior of the EP80579:
• “–” means the operation is not supported by the EP80579.
• “S” implies that the operation happens as a single atomic¹ update to memory. In
other words, either the update is observable in its entirety or not at all.
• “M” implies that the operation may happen as multiple updates to memory. In
other words, other agents can observe different parts of the affected memory
location change values in any order but the end state of the memory location will
be the desired value. This “flickering lights” effect makes such memory accesses
useless for multi-agent synchronization unless a semaphore or flag variable is used
to guard access to the shared location².
This table only applies to aligned-to-size operations; that is, a 4-byte operation is
aligned to a 4-byte boundary, an 8-byte operation is aligned to an 8-byte boundary,
etc.)
1. In the sense that it cannot be divided into multiple smaller writes.
2. Note that in guarding the location, visibility of the new flag must imply that the “flickering” has stopped.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
117