EP80579 Datasheet, PDF (144/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
5.3.5
Unit-Level Errors from the FSB Interface
The FSB interface captures error events from the FSB interface that connects the IA-32
core to the IMCH in the FSB_FERR and FSB_NERR registers. The FSB interface reports
an error event to the IA-32 core through SCI, SMI, SERR, or MCERR signals based on
the settings in the FSB_SCICMD, FSB_SMICMD, FSB_SERRCMD, and FSB_MCERRCMD
registers. Software can independently configure the specific signal that each buffer unit
error event uses.
.
Table 5-4.
Table 5-4 summarizes the error conditions that the FSB can generate.
Summary of IMCH FSB Error Conditions
Event
Type
Fatality^a
Reports via^b
Notes
Outgoing I/O Data
Parity
Outgoing Memory
Data Parity
FSB BINIT#
Detected
FSB MCERR#
Detected
Non-DRAM Lock
Error
FSB Addr. Above
TOM/TOLM
FSB Data Parity
FSB Addr. Strobe
Glitch Detected
FSB Data Strobe
Glitch Detected
FSB Request/Addr
Parity
Uncorrectable
Uncorrectable
Uncorrectable
Uncorrectable
Uncorrectable
Uncorrectable
Uncorrectable
Uncorrectable
Uncorrectable
Uncorrectable
Non-Fatal
Non-Fatal
Fatal
Non-Fatal
Non-Fatal
Non-Fatal
Non-Fatal
Fatal
Fatal
Fatal
SCI, MCERR, Parity error on outgoing data from I/O
SMI, or SERR subsystem.
SCI, MCERR, Parity error on outgoing data from
SMI, or SERR memory subsystem.
N/A^c
Electrical high-to-low transition of
BINIT#.
SCI, MCERR, Electrical high-to-low transition of
SMI, or SERR MCERR# when CMI is not driving.
SCI, MCERR, Lock detected to memory space that
SMI, or SERR does not map to DRAM.
SCI, MCERR,
SMI, or SERR
N/A^c
Address detected above TOM/TOLM.
Parity error on FSB detected.
N/A^c
Glitch detected on FSB address strobe.
N/A^c
N/A^c
Glitch detected on FSB data strobe.
Party error on FSB address or request
signals.
a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR.
b. Based on FSB_SCICMD, FSB_SMICMD, FSB_SERRCMD, and FSB_MCERRCMD register values.
c. Although the IMCH supports these errors, the EP80579 will not ever generate them since its on-die FSB
implementation does not support BINIT# or parity.
Table 5-5 summarizes the capabilities of the FSB error handling for each of the features
that the unit is expected to provide.
Table 5-5.
Summary of IMCH FSB Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The FSB_EMASK FSB_SCICMD, FSB_SMICMD, FSB_SERRCMD, and FSB_MCERRCMD
registers enable and mask error reporting.
The PCICMD register also enables and masks SERR signals.
Logging Details
FSB does not capture error logging information beyond the event flags in the FSB_FERR,
FSB_NERR and PCISTS
Reporting Multiple The FSB_NERR register captures “next” errors. This register indicates up to one additional
Errors
error (beyond the first error) of each type.
Data Poisoning FSB passes along error information to poison data.
Although the IMCH supports all of the errors Table 5-4 lists with the features in
Table 5-5, the EP80579 implementation does not take full advantage of these
capabilities since its FSB implementation does not support all of the features necessary.
Intel^® EP80579 Integrated Processor Product Line Datasheet
144
August 2009
Order Number: 320066-003US