EP80579 Datasheet, PDF (853/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.3.1.1
Offset 00h: HCAP – HBA Capabilities Register
This register indicates basic capabilities of the HBA to driver software. The RWO bits in
this register are only cleared upon PLTRST#.
Table 23-50. Offset 00h: HCAP – HBA Capabilities Register (Sheet 1 of 2)
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 00h
Offset End: 03h
Size: 32 bit
Default: Variable
Power Well: Core
Bit Range
31
30
29
28
27
26
25
24
23 : 20
Bit Acronym
Bit Description
Sticky
S64A
SCQA
SSNTF
SIS
SSS
SALP
SAL
SCLO
ISS
Supports 64-bit Addressing (S64A): Indicates the S-ATA
controller can access 64-bit data structures. The 32-bit upper
bits of the port DMA Descriptor, the PRD Base, and each PRD
entry are read/write.
Supports Native Command Queuing Acceleration
(SCQA): Indicates the SATA controller supports Serial-ATA
native command queuing. The HBA will handle DMA Setup
FISes natively and will handle the auto-activate optimization
through the FIS.
Supports SNotifiation Register (SSNTF): The SATA
controller supports the SNotification register.
Supports Interlock Switch (SIS): Indicates whether the
S-ATA controller supports interlock switches on its ports for
use in hot plug operations. This value is loaded by platform
BIOS prior to OS initialization.
If this bit is set, BIOS must also map the SATAGP pins to the
S-ATA controller through GPIO space.
Supports Staggered Spin-up (SSS): Indicates whether
the S-ATA controller supports staggered spin-up on its ports,
for use in balancing power spikes. This value is loaded by
platform BIOS prior to OS initialization.
Supports Aggressive Link Power Management (SALP):
Indicates the S-ATA controller supports auto-generating link
requests to the partial or slumber states when there are no
commands to process.
Supports Activity LED (SAL): Indicates the S-ATA
controller supports a single output pin (SATALED#) which
indicates activity.
Supports Command List Override (SCLO): When set to
'1', indicates that the HBA supports the PxCMD.CLO bit and
it's associated function. When cleared to '0', The HBA is not
capable of clearing the BSY and DRQ bits in the Status
register in order to issue a software reset if these bits are still
set from a previous operation.
Interface Speed Support (ISS): Indicates the maximum
speed the S-ATA controller can support is 1.5 Gbps and 3
Gbps on its ports. Speed can be limited in each port by
programming PxSCTL.DET to a lower value.
Bit Reset
Value
1h
1h
1h
1h
1h
1h
1h
1h
2h
Bit Access
RO
RWO
RWO
RWO
RWO
RWO
RO
RWO
RWO
19
SNZO
Supports Non-Zero DMA Offsets (SNZO): Reserved as
per AHCI 1.0
18
Reserved Reserved
17
Reserved Reserved: BIOS must clear this bit.
16
Reserved Reserved
15
PMD
PIO Multiple DRQ Block (PMD): The SATA controller
support PIO Multiple DRQ Command Block.
0h
RO
0h
RO
1h
RWO
0h
RO
1h
RWO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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