EP80579 Datasheet, PDF (996/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-30. Offset 6Ch: ULSCS - USB 2.0 Legacy Support Control/Status Register (Sheet 2
of 3)
Description: Lockable: Suspend well, and not D3-to-D0 warm reset nor core well.
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 6Ch
Offset End: 6Fh
Size: 32bit
Default: 00000000h
Power Well: Suspend
Bit Range
20
19
18
17
16
15
14
13
12 :06
05
04
03
Bit Acronym
Bit Description
Sticky
SMI_HSE
SMI on Host System Error: Shadow bit of Host System
Error bit in the USB 2.0STS. To clear this bit, system
software must write a one to the Host System Error bit in
the USB 2.0STS register.
SMI_FLR
SMI on Frame List Rollover: Shadow bit of Frame List
Rollover bit in the USB 2.0STS register. To clear this bit,
system software must write a one to the Frame List
Rollover bit in the USB 2.0STS register.
SMI_PCD
SMI on Port Change Detect: Shadow bit of Port Change
Detect bit in the USB 2.0STS register. To clear this bit,
system software must write a one to the Port Change
Detect bit in the USB 2.0STS register.
SMI_USBER
SMI on USB Error: Shadow bit of USB Error Interrupt
(USBERRINT) bit in the USB 2.0STS register. To clear this
bit, system software must write a one to the USB Error
Interrupt bit in the USB 2.0STS register.
SMI_USBC
SMI on USB Complete: Shadow bit of USB Interrupt
(USBINT) bit in the USB 2.0STS register. To clear this bit,
system software must write a one to the USB Interrupt bit
in the USB 2.0STS register.
SMI_BAREN
SMI on BAR Enable:
0 = Disable.
1 = Enable. When this bit is 1 and SMI on BAR
(D29:F7:6Ch, bit 31) is 1, then the host controller
will issue an SMI.
SMI_PCIEN
SMI on PCI Command Enable:
0 = Disable.
1 = Enable. When this bit is 1 and SMI on PCI Command
(D29:F7:6Ch, bit 31) is 1, then the host controller
will issue an SMI.
SMI_OSEN
SMI on OS Ownership Enable:
0 = Disable.
1 = Enable. When this bit is a 1 AND the OS Ownership
Change bit (D29:F7:6Ch, bit 29) is 1, the host
controller will issue an SMI.
Reserved Reserved. Hardwired to 0.
SMI_AAEN
SMI on Async Advance Enable:
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Async
Advance bit (D29:F7:6Ch, bit 21) is a 1, the host
controller will issue an SMI immediately.
SMI_HSEN
SMI on Host System Error Enable:
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Host
System Error (D29:F7:6Ch, bit 20) is a 1, the host
controller will issue an SMI.
SMI_FLREN
SMI on Frame List Rollover Enable:
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Frame
List Rollover bit (D29:F7:6Ch, bit 19) is a 1, the host
controller will issue an SMI.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
00h
0h
0h
0h
Bit Access
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
996
August 2009
Order Number: 320066-003US