EP80579 Datasheet, PDF (1079/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.5
Dynamic Processor Clock Control
27.5.1
Overview
CMI has primary control for dynamically starting and stopping system clocks. The clock
control is used for the transitions among the various S0/Cx states (i.e., IA 32 core
throttling). Each dynamic clock control method is described in this section. The various
Sleep states may also perform types of non-dynamic clock control, and are described in
Section 27.4.
CMI supports the ACPI C0, C1 and C2 states
The Dynamic Clock control is handled using the following signals:
• STPCLK# - Used to halt the IA 32 core instruction stream
The C1 state is entered based on the IA 32 core performing an autohalt instruction.
The C2 state is entered based on the IA 32 core reading the Level 2 register.
The C1, and C2 states end due to a Break event. Based on the break event, CMI
returns the system to a C0 state. Table 27-28 lists the possible break events from the
C2, states.
Table 27-28. Break Events
Event
Any unmasked interrupt goes active
Any internal event that will cause an
NMI or SMI#
Any internal event that will cause
INIT# to go active
RTC Interrupt Pending
CPU Pending Break Event Indication
REQ-C0 message from IMCH
Breaks
From
C2
C2
C2
C2
C2
C2
Comment
IRQ[0:15] when using the 8259s, IRQ[0:23] for I/O (x)
APIC. Since SCI is an interrupt, any SCI will also be a
break event.
Many possible sources
Could be indicated by the keyboard controller via the
RCIN input signal.
Only available if the RTC Interrupt (IRQ8) is enabled as
a break event (See RTC Interrupt Break Enable bit in
Section 29.3.1.1).
Only available if FERR# is enabled for break event
indication (See FERR# MUX Enable bit in
Section 29.3.1.1)
Can be sent at any time after the Ack-C2 message and
before the Ack-C0 message (i.e., any time not in C0
state).
The Pending Break Event (PBE) indication from the IA 32 core is supported using the
FERR# signal. The following rules apply:
1. When STPCLK# is detected active by the IA 32 core, the FERR# signal from the IA
32 core will be redefined to indicate whether an interrupt is pending. The signal is
active low (i.e., FERR# will be low to indicate a pending interrupt).
2. When the STPCLK# asserts, it will latch the current state of the FERR# signal and
continue to present this state to the FERR# state machine (independent of what
the FERR# pin does after the latching).
3. When the Stop-Grant cycle is detected, it will start looking at the FERR# signal as a
break event indication. If FERR# is sampled low, a break event is indicated. This
will force a transition to the C0 state.
4. When the IA 32 core detects the deassertion of STPCLK#, the IA 32 core will start
driving the FERR# signal with the natural value (i.e., the value it would do if the pin
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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