EP80579 Datasheet, PDF (1263/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 35-41. Offset 0000h: IOADDR - IOADDR Register
Description:
View: PCI 1
BAR: IOBAR
Bus:Device:Function: M:0:0
Offset Start: 0000h
Offset End: 0003h
View: PCI 2
BAR: IOBAR
Bus:Device:Function: M:1:0
Offset Start: 0000h
Offset End: 0003h
View: PCI 3
BAR: IOBAR
Bus:Device:Function: M:2:0
Offset Start: 0000h
Offset End: 0003h
Size: 32 bit
Default: 0000000h
Power Well: Vcc
Bit Range
31 : 17
16 : 00
Bit Acronym
Bit Description
Sticky
Reserved
IOADDR
Reserved
Address for I/O Operation: Provides the address for
accesses to the GbE internal registers and memories allows
access to full 128KB of space.
Bit Reset
Value
0000h
00000h
Bit Access
RO
RW
The IOADDR register must always be written as a DWORD access. Writes that are less
than 32 bits will be ignored. Reads of any size will return a DWORD of data. However,
the chipset or CPU may only return a subset of that DWORD. IOADDR must be DWORD
aligned.
Because only a particular range is addressable, the upper bits of this register are hard
coded to zero. Bits 31 through 17 are not write-able and always read back as 0b.
At hardware reset, this register value resets to 00000000h. Once written, the value is
retained until the next write or reset.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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