EP80579 Datasheet, PDF (583/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.70 Offset 130h: RPERRMSTS - Root (Port) Error Message Status Register
This register reports the status of errors received by the root complex. Each correctable
and uncorrectable (nonfatal and fatal) error source has a First Error bit and a Next
Error bit. When an error is received by the root complex, the associated First Error bit is
set and the Requestor ID is logged in the Error Source Identification register. Software
may clear an error status bit by writing a ‘1’ to the bit location. If software does not
clear the first reported error before another error is received, the Next Error status bit
is set, but the Requestor ID of the subsequent error message is discarded. These bits
are sticky through reset.
Table 16-209.Offset 130h: RPERRMSTS - Root (Port) Error Message Status Register (Sheet
1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 130h
Offset End: 133h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 130h
Offset End: 133h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 27
26 : 07
06
05
04
Bit Acronym
Bit Description
Sticky
AEIMN
Advanced Error Interrupt Message Number: If this
function has been allocated more than one MSI interrupt
number, this field reflects the offset between the base
Message Data and the MSI Message that is generated
when any of the status bits of this capability are set.
Reserved Reserved
FEMD
Fatal Error Messages Detected: This bit is used by error
handling software to determine whether fatal errors are
outstanding in the hierarchy. In hardware, this bit along
with bits 4 and 2 is used to clear fatal error escalation.
These bits are sticky through system reset.
Y
0 = Software clears this bit by writing a ‘1’ to the bit
location.
1 = Fatal error message detected.
NFEMD
Non-Fatal Error Messages Detected: This bit is used by
error handling software to determine whether non-fatal
errors are outstanding in the hierarchy. In hardware, this
bit along with bits 4 and 2 is used to clear non-fatal error
escalation. These bits are sticky through system reset.
Y
0 = Software clears this bit by writing a ‘1’ to the bit
location.
1 = Non-fatal error message detected.
FUFF
First Uncorrectable Fatal Flag: This bit captures the
nature of the first uncorrectable error message detected
(and logged in the error source ID register). These bits are
sticky through system reset.
0 = First uncorrectable error is non-fatal.
1 = First uncorrectable error is fatal.
Y
Software uses this flag to determine whether the
uncorrectable error source ID belongs to the fatal or non-
fatal error handler routine in the event that the two are
independent.
Bit Reset
Value
0h
000000h
0b
0b
0b
Bit Access
RO
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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