EP80579 Datasheet, PDF (1403/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

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explicit data pattern, and then to assert a signal to wake-up the system. In the earlier
generations, this was accomplished by using a special signal that ran across a cable to
a defined connector on the motherboard. The NIC would assert the signal for
approximately 50ms to signal a wakeup. In more recent implementations, the PCI
PME# signal has been used to wake-up the system.
On power-up, the APM Enable bits from the EEPROM Initialization Control Word 2 are
read into the APM Enable (APME) bits of the Wakeup Control Register (WCR). These bits
control enabling of APM Wakeup.
When APM Wakeup is enabled, the controller checks all incoming packets for “Magic
Packets”.
Once a matching magic packet is received, the following occurs:
• If the Assert PME On APM Wakeup (APMPME) bit is set in the Wake Up Control
Register (WUCR):
— set the PME_Status bit in the Power Management Control / Status Register
(PMCSR) and assert GBE_PME_WAKE.
• Set the Magic Packet Received bit in the Wake Up Status Register (WUS).
The controller will assert GBE_PME_WAKE until the driver does one of the following:
• clears the Magic Packet Received AMAG bit in the Wake Up Status Register (WUS)
• clears the Assert PME On APM Wakeup (APMPME) bit in the Wake Up Control
Register (WUC)
• disables APM Wakeup.
“APM Wakeup” is supported in all power states and only disabled if a subsequent
EEPROM read results in the APM Wake Up bit being cleared or the software explicitly
writes a 0 to the APM Wake Up (APM) bit of the WUC register.
37.5.10.2 ACPI Power Management Wakeup
Three sources of ACPI Power Management based Wakeups are supported:
• Reception of a “Magic Packet”.
Reception of a Network Wakeup Packet.
Activating ACPI Power Management Wakeup requires the following steps:
• The driver programs the Wake Up Filter Control Register (WUFC) to indicate the
packets it wishes to wake up and supplies the necessary data to the IPv4/v6
Address Table (IP4AT, IP6AT) and the Flexible Filter Mask Table (f), Flexible Filter
Length Table (FFLT), and the Flexible Filter Value Table (FFVT). The OS writes a 1 to
the Pme_En bit of the Power Management Control / Status Register (PMCSR.8).
Normally, after enabling wakeup, the OS will write (11)b to the lower two bits of the
PMCSR to put the GbE controller into low-power mode.
Once Wakeup is enabled, the controller monitors incoming packets, first filtering them
according to its standard address filtering method, then filtering them with all of the
enabled wakeup filters. If a packet passes both the standard address filtering and at
least one of the enabled wakeup filters, the controller will:
• Set the PME_Status bit in the Power Management Control / Status Register
(PMCSR)
• If the PME_En bit in the Power Management Control / Status Register (PMCSR) is
set, assert GBE_PME_WAKE.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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