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EP80579 Datasheet, PDF (652/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line | |||
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Intel® EP80579 Integrated Processor
Table 16-296.Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers
Mapped Through EDMALBAR Memory BAR (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h
64h
68h
6Ch
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
03h
07h
0Bh
0Fh
13h
17h
1Bh
1Fh
23h
27h
2Bh
2Fh
43h
47h
4Bh
4Fh
53h
57h
5Bh
5Fh
63h
67h
6Bh
6Fh
83h
87h
8Bh
8Fh
93h
97h
9Bh
9Fh
A3h
A7h
âOffset 00h: CCR0 - Channel 0 Channel Control Registerâ on page 653
00000000h
âOffset 04h: CSR0 - Channel 0 Channel Status Registerâ on page 656
00000000h
âOffset 08h: CDAR0 - Channel 0 Current Descriptor Address Registerâ on page 657 00000000h
âOffset 0Ch: CDUAR0 - Channel 0 Current Descriptor Upper Address Registerâ on
page 658
00000000h
âOffset 10h: SAR0 - Channel 0 Source Address Registerâ on page 658
00000000h
âOffset 14h: SUAR0 - Channel 0 Source Upper Address Registerâ on page 659
00000000h
âOffset 18h: DAR0 - Channel 0 Destination Address Registerâ on page 659
00000000h
âOffset 1Ch: DUAR0 - Channel 0 Destination Upper Address Registerâ on page 660 00000000h
âOffset 20h: NDAR0 - Channel 0 Next Descriptor Address Registerâ on page 661 00000000h
âOffset 24h: NDUAR0 - Channel 0 Next Descriptor Upper Address Registerâ on
page 662
00000000h
âOffset 28h: TCR0 - Channel 0 Transfer Count Registerâ on page 662
00000000h
âOffset 2Ch: DCR0 - Channel 0 Descriptor Control Registerâ on page 663
00000000h
âOffset 40h: CCR1 - Channel 1 Channel Control Registerâ on page 665
00000000h
âOffset 44h: CSR1 - Channel 1 Channel Status Registerâ on page 665
00000000h
âOffset 48h: CDAR1 - Channel 1 Current Descriptor Address Registerâ on page 665 00000000h
âOffset 4Ch: CDUAR1 - Channel 1 Current Descriptor Upper Address Registerâ on
page 666
00000000h
âOffset 50h: SAR1 - Channel 1 Source Address Registerâ on page 666
00000000h
âOffset 54h: SUAR1 - Channel 1 Source Upper Address Registerâ on page 666
00000000h
âOffset 58h: DAR1 - Channel 1 Destination Address Registerâ on page 667
00000000h
âOffset 5Ch: DUAR1 - Channel 1 Destination Upper Address Registerâ on page 667 00000000h
âOffset 60h: NDAR1 - Channel 1 Next Descriptor Address Registerâ on page 667 00000000h
âOffset 64h: NDUAR1 - Channel 1 Next Descriptor Upper Address Registerâ on
page 668
00000000h
âOffset 68h: TCR1 - Channel 1 Transfer Count Registerâ on page 668
00000000h
âOffset 6Ch: DCR1 - Channel 1 Descriptor Control Registerâ on page 668
00000000h
âOffset 80h: CCR2 - Channel 2 Channel Control Registerâ on page 669
00000000h
âOffset 84h: CSR2 - Channel 2 Channel Status Registerâ on page 669
00000000h
âOffset 88h: CDAR2: Channel 2 Current Descriptor Address Registerâ on page 669 00000000h
âOffset 8Ch: CDUAR2 - Channel 2 Current Descriptor Upper Address Registerâ on
page 670
00000000h
âOffset 90h: SAR2 - Channel 2 Source Address Registerâ on page 670
00000000h
âOffset 94h: SUAR2 - Channel 2 Source Upper Address Registerâ on page 670
00000000h
âOffset 98h: DAR2 - Channel 2 Destination Address Registerâ on page 671
00000000h
âOffset 9Ch: DUAR2 - Channel 2 Destination Upper Address Registerâ on page 671 00000000h
âOffset A0h: NDAR2 - Channel 2 Next Descriptor Address Registerâ on page 671 00000000h
âOffset A4h: NDUAR2 - Channel 2 Next Descriptor Upper Address Registerâ on
page 672
00000000h
Intel® EP80579 Integrated Processor Product Line Datasheet
652
August 2009
Order Number: 320066-003US
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