EP80579 Datasheet, PDF (1165/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
32.3.3
32.3.3.1
Warning:
32.3.3.2
Warning:
Periodic vs. Non-Periodic Modes
Non-Periodic Mode
This mode can be thought of as creating a one-shot.
Timer 0 is configurable to 32-bit or 64-bit mode (default), whereas Timers 1 and 2 only
support 32-bit mode.
All three timers support non-periodic mode.
When a timer is set up for non-periodic mode, it generates a value in the main counter
that matches the value in the timer’s comparator register. Also, another interrupt will
be generated when the main counter matches the value in the timer’s comparator
register after a wrap around.
During run-time, the value in the timer’s comparator value register is not changed by
the hardware. Software can, of course, change the value.
The Timer 0 Comparator Value register cannot be programmed reliably by a single 64-
bit write in a 32-bit environment except if only the periodic rate is being changed
during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then
the following software solution always works regardless of the environment:
1. Set the lower 32 bits of the Timer0 Comparator Value register.
2. Set the upper 32 bits of the Timer0 Comparator Value register.
Software must be careful when programming the comparator registers. If the value
written to the register is not sufficiently far in the future, then the counter may pass
the value before it reaches the register and the interrupt will be missed. The BIOS will
pass a data structure to the OS to indicate that the OS must not attempt to program
the periodic timer to a rate faster then X. For the CMI, X is 5 microseconds.
Every timer is required to support the non-periodic mode of operation.
Periodic Mode
When a timer is set up for periodic mode, the software writes a value in the timer’s
comparator value register. When the main counter value matches the value in the
timer’s comparator value register, an interrupt is generated. The hardware then
automatically increases the value in the comparator value register by the last value
written to that register.
To make the periodic mode work properly, the main counter is typically written with a
value of 0 so that the first interrupt occurs at the right point for the comparator. If the
main counter is not set to 0, interrupts may not occur as expected.
During run-time, the value in the timer’s comparator value register can be read by
software to find out when the next periodic interrupt will be generated (not the rate at
which it generates interrupts). Software is expected to remember the last value written
to the comparator’s value register (the rate at which interrupts are generated).
If software wants to change the periodic rate, it must write a new value to the
comparator value register. At the point when the timer’s comparator indicates a match,
this new value is added to derive the next matching point.
If the software resets the main counter, the value in the comparator’s value register
needs to reset as well. This can be done by setting the TIMERn_VAL_SET_CNF bit.
Again, to avoid race conditions, this must be done with the main counter halted. As the
timer period approaches zero, the interrupts associated with the periodic timer may not
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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