EP80579 Datasheet, PDF (72/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
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26-55
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26-57
Offset 02h: DID - Device Identification Register .................................................... 979
Offset 04h: CMD - Command Register ............................................................... 980
Offset 06h: DSR - Device Status Register ........................................................... 981
Offset 08h: RID - Revision ID Register................................................................. 983
Offset 09h: PI - Programming Interface Register................................................... 983
Offset 0Ah: SCC - Sub Class Code Register .......................................................... 983
Offset 0Bh: BCC - Base Class Code Register ......................................................... 984
Offset 0Dh: MLT - Master Latency Timer Register .................................................. 984
Offset 10h: MBAR - Memory Base Address Register ............................................... 985
Offset 2Ch: SSVID - USB 2.0 Subsystem Vendor ID Register .................................. 985
Offset 2Eh: SSID - USB 2.0 Subsystem ID Register ............................................... 986
Offset 34h: CAP_PTR - Capabilities Pointer Register............................................... 986
Offset 3Ch: ILINE - Interrupt Line Register........................................................... 987
Offset 3Dh: IPIN - Interrupt Pin Register.............................................................. 987
Offset 50h: PM_CID - PCI Power Management Capability ID Register ....................... 987
Offset 51h: PM_NEXT - Next Item Pointer #1 Register ........................................... 988
Offset 52h: PM_CAP - Power Management Capabilities Register ............................ 989
Offset 54h: PM_CS - Power Management Control/Status Register .......................... 990
Offset 58h: DP_CID - Debug Port Capability ID Register......................................... 991
Offset 59h: DP_NEXT - Next Item Pointer #2 Register ........................................... 991
Offset 5Ah: DP_BASE - Debug Port Base Offset Register ........................................ 991
Offset 60h: SBRN - Serial Bus Release Number Register ...................................... 992
Offset 61h: FLA - Frame Length Adjustment Register ........................................... 992
Offset 62h: PWC - Port Wake Capability Register ................................................. 993
Offset 64h: CUO - Classic USB Override Register .................................................. 994
Offset 68h: ULSEC - USB 2.0 Legacy Support Extended Capability Register ............ 994
Offset 6Ch: ULSCS - USB 2.0 Legacy Support Control/Status Register ................... 995
Offset 70h: ISU2SMI - Intel Specific USB 2.0 SMI Register ................................... 997
Offset 80h: AC - Access Control Register ............................................................ 999
Offset F8h: MANID - Manufacturer ID Register .................................................. 1000
Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller Configuration Registers
Mapped Through MBAR Memory BAR ................................................................. 1001
Offset 00h: CAPLENGTH - Capability Length Register ........................................... 1002
Offset 02h: HCIVERSION - Host Controller Interface Version Number Register ........ 1003
Offset 04h: HCSPARAMS - Host Controller Structural Parameters Register ............ 1003
Offset 08h: HCCPARAMS - Host Controller Capability Parameters Register ............ 1004
Host Controller Operational Register Details Summary Table ................................ 1006
Offset 20h: USB2CMD - USB 2.0 Command Register ......................................... 1007
Offset 24h: USB2STS - USB 2.0 Status Register ................................................ 1009
Offset 28h: USB2INTR - USB 2.0 Interrupt Enable Register ................................ 1012
Offset 2Ch: FRINDEX - Frame Index Register ................................................... 1013
Offset 30h: CTRLDSSEGMENT - Control Data Structure Segment Register .............. 1014
Offset 34h: PERIODICLISTBASE - Periodic Frame List Base Address Register ........ 1014
Offset 38h: ASYNCLISTADDR - Current Asynchronous List Address Register ......... 1015
Offset 60h: CONFIGFLAG - Configure Flag Register ............................................ 1015
Offset 64h: PORTSC - Port N Status and Control Register .................................... 1016
HCRESET Bit Summary ................................................................................... 1021
Periodic DMA Engine Memory Reads ................................................................. 1022
Asynchronous DMA Engine Reads ..................................................................... 1025
Asynchronous DMA Engine Writes .................................................................... 1027
Host Interface Parity Errors ............................................................................. 1028
Effect of Resets on Port-Routing Logic ............................................................... 1035
Offset A0h: CNTL_STS - Control/Status Register ............................................... 1037
Offset A4h: USBPID - USB PIDs Register .......................................................... 1039
Offset A8h: DATABUF - Data Buffer Bytes 7:0 ................................................... 1039
Intel^® EP80579 Integrated Processor Product Line Datasheet
72
August 2009
Order Number: 320066-003US