EP80579 Datasheet, PDF (1606/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
40.4
Register Summary
There are five registers in the SSP block: two control, one data, one status register, and
one test register.
• Control registers are used to program the baud rate, data length, frame format,
data transfer mechanism, and port enabling. In addition, they permit setting the
FIFO “fullness” threshold that will trigger an interrupt.
• The Data Register is mapped as one 32-bit location, which physically points to
either of two 32-bit registers. One register is for WRITES, and transfers data to the
Transmit FIFO; the other is for READS, and takes data from the Receive FIFO. A
write cycle, will load successive words into the SSP Write Register, from the lower
half 2 bytes of a 32-bit word to the Transmit FIFO. A READ cycle, will similarly take
data from the SSP Read Register, and the Receive FIFO will reload it with available
data bits it has stored.
The FIFOs are independent buffers that allow full duplex operation.
• The Status Register signals the state of the FIFO buffers: whether the
programmable threshold has been passed (Transmit/Receive Buffer service
request), and a value showing the actual “fullness” of the FIFO. There are flag bits
to indicate when the SSP is actively transmitting data, when the Transmit Buffer is
not full, and when the Receive Buffer is not empty. Error bits signal overrun errors.
The SSP registers materialize in the PCI space.
Table 40-1 summarizes the SSP materialization from the PCI perspective.
Table 40-1. Bus M, Device 6, Function 0: Summary of SSP CSRs
Offset Start Offset End
Register ID - Description
00h
03h
“Offset 00h: SSCR0 - SSP Control Register 0 Details” on page 1607
04h
07h
“Offset 04h: SSCR1 - SSP Control Register 1 Details” on page 1610
08h
0Bh
“Offset 08h: SSSR - SSP Status Register Details” on page 1614
0Ch
0Fh
“Offset 0Ch: SSITR - SSP Interrupt Test Register Details” on page 1617
10h
13h
“Offset 10h: SSDR - SSP Data Register Details” on page 1618
Default
Value
00000000h
00000000h
0000F004h
00000000
00000000h
Intel^® EP80579 Integrated Processor Product Line Datasheet
1606
August 2009
Order Number: 320066-003US