EP80579 Datasheet, PDF (212/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-25. Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management
General Configuration Registers Mapped Through PMBASE I/O BAR (Sheet 2
of 2)
Offset Start Offset End
Register ID - Description
Default
Value
30h
30h
“Offset 30h: SMI_EN - SMI Control and Enable Register” on page 1068
00000000h
34h
34h
“Offset 34h: SMI_STS - SMI Status Register” on page 1071
00000000h
38h
38h
“Offset 38h: ALT_GPI_SMI_EN - Alternate GPI SMI Enable Register” on page 1073 0000h
3Ah
3Ah
“Offset 3Ah: ALT_GPI_SMI_STS - Alternate GPI SMI Status Register” on page 1074 0000h
44h
44h
“Offset 44h: DEVTRAP_STS - DEVTRAP_STS Register” on page 1074
0000h
Table 7-26. Bus 0, Device 31, Function 0: Summary of General Purpose I/O Configuration
Registers Mapped Through GBA BAR IO BAR
Offset Start Offset End
Register ID - Description
Default
Value
00h
03h
“Offset 00h: GPIO_USE_SEL1 - GPIO Use Select 1 {31:0} Register” on page 807 Variable
04h
07h
“Offset 04h: GP_IO_SEL1 - GPIO Input/Output Select 1 {31:0} Register” on
page 808
E400FFFFh
0Ch
0Fh
“Offset 0Ch: GP_LVL1 - GPIO Level 1 for Input or Output {31:0} Register” on
page 809
FF3F0000h
18h
1Bh
“Offset 18h: GPO_BLINK - GPIO Blink Enable Register” on page 810
00040000h
2Ch
2Fh
“Offset 2Ch: GPI_INV - GPIO Signal Invert Register” on page 812
00000000h
30h
33h
“Offset 30h: GPIO_USE_SEL2 - GPIO Use Select 2 {63:32} Register” on page 813 Variable
34h
37h
“Offset 34h: GP_IO_SEL2 - GPIO Input/Output Select 2 {63:32} Register” on
page 813
00000300h
38h
3Bh
“Offset 38h: GP_LVL2 - GPIO Level for Input or Output 2 {63:32} Register” on
page 814
00030207h
Intel^® EP80579 Integrated Processor Product Line Datasheet
212
August 2009
Order Number: 320066-003US