EP80579 Datasheet, PDF (1050/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-4. Offset A2h: GEN_PMCON_2 - General PM Configuration 2 Register (Sheet 2 of
2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: A2h
Offset End: A2h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
MAWVS
Minimum SLP_S4# Assertion Width Violation Status:
0 = Software clears this bit by writing a 1 to it.
1 = Hardware sets this bit when the SLP_S4# assertion
width is less than the time programmed in the
SLP_S4# Minimum Assertion Width field
(D31.F0.A4h.5:4). When exiting G3, the timer begins
when the RSMRST# input deasserts.
Note: This bit is functional regardless of the value in the
SLP_S4# Assertion Stretch Enable. This bit is
reset by the assertion of the RSMRST# pin, but
can be set in some cases before the default value
is readable.
CPUPWR_FLR
CPU Power Failure:
0 = Software (typically) BIOS clears this bit by writing a 0
to it.
1 = Indicates that the VRMPWRGD input signal (/) from
the processor’s VRM went low.
Note: VRMPWRGD is sampled using the RTC clock.
Therefore, low times that are less than one RTC
clock period may not be detected.
PWROK_FLR
Power OK Failure:
0 = Software clears this bit by writing a 1 to it, or when
the system goes into a G3 state.
1 = This bit will be set any time PWROK goes low, when
the system was in S0, or S1 state. The bit will be
cleared only by software by writing a 1 to this bit or
when the system goes to a G3 state.
See Section 27.6.3 for more details about the PWROK pin
functionality.
Note: In the case of true PWROK failure, PWROK will go
low first before the VRMPWRGD.
Bit Reset
Value
0h
0h
0h
Bit Access
RWC
RW
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1050
August 2009
Order Number: 320066-003US