EP80579 Datasheet, PDF (563/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-189.Offset 74h: PEALNKCTL - PCI Express Link Control Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 74h
Offset End: 75h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 74h
Offset End: 75h
Size: 16 bit
Default: 0001h
Power Well: Core
Bit Range
05
04
Bit Acronym
Bit Description
Sticky
Retrain Link:
0 = Link retraining not initiated. This bit always returns 0
RL
when read.
1 = Link retraining initiated
Note: Link retraining does not force a “Link Down”
condition, it merely invokes “recovery.”
Link Disable: Disables/Enables the associated PCI
Express* link.
LD
0 = Enable
1 = Disable
Bit Reset
Value
0b
0b
Bit Access
WO
RW
03
02
01 : 00
RCB
Reserved
ASLPMC
Read Request Return parameter “R” Control:
Hardwired to ‘0’, indicating “RCB” capability of 64B. This is
also known as Read Completion Boundary.
Reserved
Active State Link PM Control: Controls the level of
active state power management supported on the
associated PCI Express* link.
Defined encodings are:
00b Disabled
01b L0s Entry Supported
10b Reserved
11b Reserved
0b
RO
0b
01b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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