EP80579 Datasheet, PDF (815/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 22-11. Offset 38h: GP_LVL2 - GPIO Level for Input or Output 2 {63:32} Register
(Sheet 2 of 2)
Description:
This register allows
when output.
reading
of
the
current
GPIO
bit
values
for
GPIO
pins
31-0
when
input,
and
writing
the
value
View: PCI
BAR: GBA(IO)
Bus:Device:Function: 0:31:0
Offset Start: 38h
Offset End: 3Bh
Size: 32 bit
Default: 00030207h
Power Well: Core
Bit Range
07 : 03
02 : 01
00
Bit Acronym
Bit Description
Sticky
Reserved Read-Only 0.
If GPIO[n] is programmed to be an output (via the
corresponding bit in the GP_IO_SEL register), then the
corresponding GP_LVL[n] bit can be updated by
software to drive a high or low value on the output pin.
If GPIO[n] is programmed as an input, then the
GP_LVL_34_33
corresponding GP_LVL bit reflects the state of the input
signal (1 = high, 0 = low). Writes have no effect.
0 = low
1 = high
Since these bits correspond to GPIO that are in the core
well and are reset to their native function by PLTRST#.
Reserved ^{Reserved. No corresponding GPIO.}
Bit Reset
Value
0h
11b
1b
Bit Access
RW
RW
22.3
22.3.1
22.3.2
Note:
Additional GPIO Theory of Operation
SMI# and SCI Routing
The routing bits for GPIO[0:15] allow an input to be routed to SMI# or SCI, or neither.
See Chapter 40, “Power Management” for the routing register. A bit can be routed to
either an SMI# or an SCI, but not both.
Triggering
GPIO[0:15] have “sticky” bits on the input. See Chapter 40, “Power Management” for
the GPE0_STS register and the ALT_GPI_SMI_STS register. As long as the signal goes
active for at least two clocks (PCI clock while in S0-S1 state, RTC clock while in S3-S5
state),CMI keeps the sticky status bit active. The active level (high or low) can be
selected via the GP_INV register.
If the system is in an S0 or S1-D state, the GPI are sampled at 33 MHz, so the signal
only needs to be active for about 60 ns to be latched. In S3,-S5 states, the GPI are
sampled at 32.768 kHz, and thus must be active for at least 61 µs to be latched.
GPIs that are in the core well are not capable of waking the system from sleep states
where the core well is not powered.
If the input signal is still active when the latch is cleared, it is again set (another edge is
not required). This makes these signals “level” triggered inputs.
§§
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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