EP80579 Datasheet, PDF (1487/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.4.13 RXCSUM – Receive Checksum Control Register
This register controls the receive checksum off loading features. The GbE supports the
off loading of three receive checksum calculations: the Packet Checksum, the IP Header
Checksum, and the TCP/UDP Checksum. Supported frame types are Ethernet II and
Ethernet SNAP. This register should only be written when the receiver is not enabled
(i.e., only when RCTL.EN = 0).
Table 37-62. RXCSUM: Receive Checksum Control Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 5000h
Offset End: 5003h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 5000h
Offset End: 5003h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 5000h
Offset End: 5003h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 : 10
09
08
07 : 00
Bit Acronym
Bit Description
Sticky
Rsvd
TUOFL
IPOFL
PCSS
Reserved
TCP/UDP Checksum Off load Enable. This bit is used to
enable the TCP/UDP Checksum off-loading feature.
0 = TCP/UDP Checksum Off load Disabled
1 = Hardware will calculate the TCP or UDP checksum and
indicate a pass/fail indication to software via the TCP/
UDP Checksum Error bit (TCPE).
IP Checksum Off load Enable. This bit is used to enable
the IP Checksum off-loading feature.
0 = IP Checksum Off load Disabled
1 = Hardware will calculate the IP checksum and indicate
a pass/fail indication to software via the IP Checksum
Error bit (IPE) in the ERROR field of the receive
descriptor.
Packet Checksum Start. This field controls the starting
byte for the Packet Checksum calculation. The Packet
Checksum is the one's complement over the receive
packet, starting from the byte indicated by PCSS (0
corresponds to the first byte of the packet), after stripping.
For example, for an Ethernet II frame encapsulated as an
802.3ac VLAN packet and with PCSS set to 14, the packet
checksum would include the entire encapsulated frame,
excluding the 14-byte Ethernet header (DA, SA, Type and
Length) and the 4-byte VLAN tag. The Packet Checksum
will not include the Ethernet CRC if the RCTL.SECRC bit is
set. Software must make the required offsetting
computation (to back out the bytes that should not have
been included and to include the pseudo-header) prior to
comparing the Packet Checksum against the TCP checksum
stored in the packet.
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RV
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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