EP80579 Datasheet, PDF (1049/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.3.1.2 Offset A2h: GEN_PMCON_2 - General PM Configuration 2 Register
Table 27-4. Offset A2h: GEN_PMCON_2 - General PM Configuration 2 Register (Sheet 1 of
2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: A2h
Offset End: A2h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
07
06 : 05
04
03
Bit Acronym
Bit Description
Sticky
DIB
RSVD
SRS
CTS
DRAM Initialization bit:
This bit does not effect hardware functionality in any
way.BIOS is expected to set this bit prior to starting the
DRAM initialization sequence and to clear this bit after
completing the DRAM initialization sequence. BIOS can
detect that a DRAM initialization sequence was interrupted
by a reset by reading this bit during the boot sequence. If
the bit is 1, then the DRAM initialization was interrupted.
See Section 27.5.1 for the expected BIOS response.
This bit is reset by the assertion of the RSMRST# pin.
Reserved
System Reset Status:
0 = SYS_RESET# button Not pressed.
1 = This bit is set when the SYS_RESET# button is
pressed. BIOS is expected to read this bit and clear it
if it is set.
Note: This bit is also reset by RSMRST# and CF9h
resets.
CPU Thermal Trip Status:
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when PLTRST# is inactive and
THRMTRIP# goes active while the system is in an S0
or S1 state.
Note: This bit is also reset by RSMRST# and CF9h
resets. It is not reset by the shutdown and reboot
associated with the CPUTHRMTRIP# event.
Bit Reset
Value
0h
00h
0h
0h
Bit Access
RW
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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