EP80579 Datasheet, PDF (1608/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 40-2. Offset 00h: SSCR0 - SSP Control Register 0 Details (Sheet 2 of 2)
Description: SSP Control Register 0
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:6:0
Offset Start: 00h
Offset End: 03h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
6
05 :04
03 :00
Bit Acronym
Bit Description
Sticky
ECS
FRF
DSS
External clock select bit.
0 = On-chip clock used to produce the SSP’s serial clock
(SSP_SCLK).
1 = SSP_EXTCLK is used to create the SSP’s
SSP_SCLK.
This field specifies the FRame Format.
00 - Motorola* Serial Peripheral Interface (SPI)
01 - Texas Instruments* Synchronous Serial Protocol
(SSP)
10 - National Microwire*
11 - Reserved, undefined operation
This field specifies the Data Size Selection.
0000 - Reserved, undefined operation
0001 - Reserved, undefined operation
0010 - Reserved, undefined operation
0011 - 4-bit data
0100 - 5-bit data
0101 - 6-bit data
0110 - 7-bit data
0111 - 8-bit data
1000 - 9-bit data
1001 - 10-bit data
1010 - 11-bit data
1011 - 12-bit data
1100 - 13-bit data
1101 - 14-bit data
1110 - 15-bit data
1111 - 16-bit data
Bit Reset
Value
0b
0h
0h
Bit Access
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1608
August 2009
Order Number: 320066-003US