EP80579 Datasheet, PDF (99/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 1-4. Glossary Table (Sheet 2 of 5)
Term
Atomic operation
Block Locking
Buffer
Cx States
Cache Line
Cfg
Character
CMI
Coherent (C)
Command
Completion
Core Power Well
Cyclic Redundancy Check
Deasserted
Deferred Transaction
Delayed Transaction
Direct Memory Access
Downstream
Definition
A series of two or more transactions to a device by the same initiator which are guaranteed to
complete without intervening accesses by a different master. Most commonly required for a
read-modify-write (RMW) operation.
Ability to lock the FWH’s blocks to write-protect, read-protect, or open state.
1. A random access memory structure. 2. The term I/O buffer is also used to describe a low-
level input receiver and output driver combination.
Processor power states (Cx states) are processor power consumption and thermal
management states within the global working state, G0.
• C0: Processor power state - While the processor is in this state, it executes instructions.
• C1: Processor power state - This power state has the lowest latency. The hardware latency
in this state must be low enough that the operating software does not consider the latency
aspect of the state when deciding whether to use it.
• C2: Processor power state - This state offers improved power savings over the C1 state.
The worst-case hardware latency for this state is provided via the ACPI system firmware
and operating software can use this information to determine when the C1 state should be
used instead of the C2 state.
• C3: Processor power state - This state is not supported. The C3 state offers improved
power savings over the C1 and C2 states. The worst-case hardware latency for this state is
provided via the ACPI system firmware and the operating software can use this information
to determine when the C2 state should be used instead of C3 state. While in the C3 state,
the processor’s caches maintain state but ignore any snoops.
The unit of memory that is copied to and individually tracked in a cache. Specifically, 64 bytes
of data or instructions aligned on a 64-byte physical address boundary.
Used as a qualifier for transactions that target PCI configuration address space.
The raw data Byte in an encoded system (i.e., the 8b value in a 8b/10b encoding scheme). This
is the meaningful quantum of information to be transmitted or that is received across an
encoded transmission path.
IA-32 Core interface, Memory controller hub, I/O controller hub
Transactions that ensure that the processor’s view of memory through the cache is consistent
with that obtained through the I/O subsystem. In EP80579 integrated processor, Coherent (C)
memory regions are coherent with IA caches when accessed from AIOC agents. Accesses to
these memory regions enter the memory system through the IMCH. Memory regions that are
coherent with IA caches must be accessible to the IA CPU.
The distinct phases, cycles, or packets that make up a transaction. Requests and Completions
are referred to generically as Commands.
A packet, phase, or cycle used to terminate a Transaction on a interface, or within a
component. A Completion will always refer to a preceding Request and may or may not include
data and/or other information.
Main system power, turns off in S3 – S5
A number derived from, and stored or transmitted with, a block of data in order to detect
corruption. By recalculating the CRC and comparing it to the value originally transmitted, the
receiver can detect some types of transmission errors.
Signal is set to a level that represents logical false.
A processor bus Split Transaction. The requesting agent receives a Deferred Response which
allows other transactions to occur on the bus. Later, the response agent completes the original
request with a separate Deferred Reply transaction.
A transaction where the target retries an initial request, but unknown to the initiator, forwards
or services the request on behalf of the initiator and stores the completion or the result of the
request. The original initiator subsequently reissues the request and receives the stored
completion.
Method of accessing memory on a system without interrupting the processors on that system.
Describes commands or data flowing away from the processor-memory complex and toward I/
O. The terms Upstream and Downstream are never used to describe transactions as a whole.
(e.g. Downstream data may be the result of an Outbound Write, or an Inbound Read. The
Completion to an Inbound Read travels Downstream.)
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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