EP80579 Datasheet, PDF (1670/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.32 Offset 0208h: UD_Header_Offset - User Defined Header Offset Register
Register
Name
UD_Header_Offset
Access
(See below.) Reset Value x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(Reserved)
UD_Offset
Table 41-42. Offset 0208h:User Defined Header Offset Register
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 00000208h
Offset End: 0000020Bh
Size: 32 bits
Default: 00000000h
Power Well: Core
Bit Range
31 : 8
7: 0
Bit Acronym
Bit Description
RSVD
UD_Offset
Reserved. Must be written as “0”
User defined offset for header
Sticky
Bit Reset
Value
0h
0h
Bit Access
RW
RW
41.6.1.33 Offset 020Ch: UD_Header - User Defined Header Register
Register
Name
UD_Header
Access
(See below.) Reset Value x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mask
UD_Header
Table 41-43. Offset 020Ch:User Defined Header Register
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 0000020Ch
Offset End: 0000020Fh
Size: 32 bits
Default: 00000000h
Power Well: Core
Bit Range
31 : 16
15 : 0
Bit Acronym
Bit Description
Mask
Mask for compare value
UD_Header User defined compare value for header
Sticky
Bit Reset
Value
0h
0h
Bit Access
RW
RW
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Intel^® EP80579 Integrated Processor Product Line Datasheet
1670
August 2009
Order Number: 320066-003US