EP80579 Datasheet, PDF (756/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
19.2.6.4 Offset DCh: BC: BIOS Control Register
Table 19-30. Offset DCh: BC: BIOS Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: DCh
Offset End: DCh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 :04
Bit Acronym
Bit Description
Sticky
Reserved
Reserved
SPI Read Configuration:
This 2-bit field controls two policies related to BIOS reads
on the SPI interface
Bit 3 - Prefetch Enable
Bit 2 - Cache Disable
Bit Reset
Value
0h
Bit Access
03 02
SRC
00b -> No prefetching, but caching enabled. 64B
demand reads load the read buffer cache with “valid”
data, allowing repeated code fetches to the same line to
complete quickly
01b -> No prefetching and no caching. One-to-one
correspondence of the host BIOS reads to SPI cycles. This
value can be used to invalidate the cache.
00h
RW
10b -> Prefetching and Caching enabled. This mode
is used for long sequences of short reads to consecutive
addresses (i.e. shadowing)
11b -> Reserved. This is an invalid configuration.
Lock Enable:
01
LE
0 = Setting the WP will not cause SMIs
1 = Enables setting the WP bit to cause SMIs. Once set,
this bit can only be cleared by a PLTRST#
Write Protect:
0 = Only read cycles result in Firmware Hub Interface
cycles
00
WP
1 = Access to the BIOS space is enabled for both read
and write cycles. When this bit is written from a 0 to
a 1 and Lock Enable (LE) is also set, an SMI# is
generated. This ensures that only SMI code can
update BIOS.
0h
RWO
0h
RW
19.2.7
19.2.7.1
Root Complex Register Block Configuration Register
Offset F0h: RCBA: Root Complex Base Address Register
RCBA sets the base address in memory space for the Root Complex Configuration
registers (see Section 17.1, “Root Complex Memory-Mapped Configuration Register
Details” on page 689). These registers can be mapped anywhere in the 32-bit memory
space on 16KB boundaries.
The SPI register space resides in this BAR. The base address offset is 3020h. Refer to
Chapter 21.0, “Serial Peripheral Interface”.
Intel^® EP80579 Integrated Processor Product Line Datasheet
756
August 2009
Order Number: 320066-003US