EP80579 Datasheet, PDF (68/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
21-10
21-11
21-12
21-13
21-14
21-15
21-16
22-1
22-2
22-3
22-4
22-5
22-6
22-7
22-8
22-9
22-10
22-11
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
23-10
23-11
23-12
23-13
23-14
23-15
Offset 8Bh: DMA_MPL[5-7]: DMA Memory Low Page Registers for Channels 5-7 ....... 771
Offset 08h: DMA_STATUS - DMA Status Register ................................................ 772
Offset 0Ah: DMA_WSM - DMA Write Single Mask Register ..................................... 773
Offset 0Bh: DMA_CHM - DMA Channel Mode Register .......................................... 774
Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register ....................................... 775
Offset 0Dh: DMA_MC - DMA Master Clear Register ............................................... 775
Offset 0Eh: DMA_CM - DMA Clear Mask Register ................................................. 776
Offset 0Fh: DMA_WAM - DMA Write All Mask Register .......................................... 777
DMA Channel Priority ........................................................................................ 778
Address Shifting in 16-bit DMA Transfers ............................................................. 779
SPI Pin Interface .............................................................................................. 785
GPIO Boot Source Selection ............................................................................... 786
SPI Cycle Timings ............................................................................................. 789
Bus 0, Device 31, Function 0, PCI Registers Mapped Through RCBA Bar ................... 789
Offset 3020h: SPIS - SPI Status ........................................................................ 790
Offset 3022h: SPIC - SPI Control ....................................................................... 791
Offset 3024h: SPIA - SPI Address ..................................................................... 792
Offset 3028h: SPID0 - SPI Data 0 ..................................................................... 792
Offset 3030h, 3038h, 3040h, 3048h, 3050h, 3058h, 3060h: SPI[0-6] -
SPI Data [0-6] ................................................................................................ 793
Offset 3070h: BBAR - BIOS Base Address .......................................................... 793
Offset 3074h: PREOP - Prefix Opcode Configuration ............................................. 794
Offset 3076h: OPTYPE - Op Code Type .............................................................. 794
Offset 3078h: OPMENU - OPCODE Menu Configuration .......................................... 795
Offset 3080h: PBR0 - Protected BIOS Range #0 .................................................. 796
Byte Enable Handling on Direct Memory Reads ..................................................... 798
Flash Protection Mechanism Summary ................................................................. 800
GPIO Pin’s Alternative Function........................................................................... 804
GPIO Summary Table ....................................................................................... 805
Bus 0, Device 31, Function 0: Summary of General Purpose I/O Configuration Registers
Mapped Through GBA BAR IO BAR ...................................................................... 806
Offset 00h: GPIO_USE_SEL1 - GPIO Use Select 1 {31:0} Register ........................ 807
Offset 04h: GP_IO_SEL1 - GPIO Input/Output Select 1 {31:0} Register ................. 808
Offset 0Ch: GP_LVL1 - GPIO Level 1 for Input or Output {31:0} Register ............... 809
Offset 18h: GPO_BLINK - GPIO Blink Enable Register .......................................... 810
Offset 2Ch: GPI_INV - GPIO Signal Invert Register .............................................. 812
Offset 30h: GPIO_USE_SEL2 - GPIO Use Select 2 {63:32} Register ....................... 813
Offset 34h: GP_IO_SEL2 - GPIO Input/Output Select 2 {63:32} Register ............... 813
Offset 38h: GP_LVL2 - GPIO Level for Input or Output 2 {63:32} Register ............. 814
Bus 0, Device 31, Function 2: Summary of SATA Controller PCI Configuration
Registers ......................................................................................................... 817
Offset 00h: ID – Identifiers Register.................................................................... 819
Offset 04h: CMD - Command Register ................................................................ 819
Offset 06h: STS - Device Status Register ............................................................ 820
Offset 08h: RID - Revision ID Register................................................................. 821
Programming Interface, DID and CC.SCC Register Value Definitions ........................ 822
Programming Interface when CC.SCC = “01h” ...................................................... 822
Programming Interface when CC.SCC = “06h” ...................................................... 823
Offset 0Ah: CC - Class Code Register .................................................................. 823
Offset 0Dh: MLT – Master Latency Timer Register ................................................. 823
Offset 10h: PCMDBA – Primary Command Block Base Address Register.................... 824
Offset 14h: PCTLBA – Primary Control Block Base Address Register ......................... 824
Offset 18h: SCMDBA – Secondary Command Block Base Address Register................ 825
Offset 1Ch: SCTLBA – Secondary Control Block Base Address Register..................... 825
Offset 20h: LBAR – Legacy Bus Master Base Address Register when SCC is SATA
Intel^® EP80579 Integrated Processor Product Line Datasheet
68
August 2009
Order Number: 320066-003US