EP80579 Datasheet, PDF (821/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-4. Offset 06h: STS - Device Status Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 02B0h
Power Well: Core
Bit Range
04
03
02 : 00
Bit Acronym
Bit Description
CL
IS
Reserved
Capabilities List (CL): Indicates the presence of a
capabilities list. The minimum requirement for the
capabilities list must be PCI power management for the
SATA Controller.
Interrupt Status (IS): Reflects the state of INTx#
messages. This bit is set when the interrupt is to be
asserted. This bit is a 0 after the interrupt is cleared
(independent of the state of CMD.ID).
Reserved
Sticky
Bit Reset
Value
1h
0h
0h
Bit Access
RO
RO
RO
23.1.1.4 Offset 08h: RID - Revision ID Register
Table 23-5. Offset 08h: RID - Revision ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 08h
Offset End: 08h
Size: 8 bit
Default: Variable
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
Revision ID (RID): Indicates stepping of the host
RID
controller hardware. This register follows the ICH revision
ID scheme as defined in Section 19.2.1.4, “Offset 08h:
RID - Revision ID Register” on page 736.
Bit Reset
Value
Variable
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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