EP80579 Datasheet, PDF (1377/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
37.5.6.7
Note:
37.5.6.8
Software can determine if a packet has been sent by either of two methods: setting the
RS bit in the transmit descriptor command field or by performing a host CPU read of the
transmit head register. Checking the transmit descriptor DD bit in memory eliminates a
potential race condition. All descriptor data is written to the host bus prior to
incrementing the head register, but a read of the head register could “pass” the data
write in systems performing write buffering. Updates to transmit descriptors use the
same write path and follow all data writes. Consequently, they are not subject to the
race.
Hardware pre-fetches the entire packet data prior to transmission, and updates the
value of the head pointer after storing each descriptor's data in the transmit FIFO.
The process of checking for completed packets consists of one of the following:
• Scan memory.
• Read the hardware head register. All packets up to but excluding the one pointed
to by head have been sent or buffered and can be reclaimed.
• Take an interrupt. An interrupt condition is generated whenever a transmit queue
goes empty (ICR.TXQE). This interrupt can either be enabled or masked.
Transmit Descriptor Fetching
The descriptor processing strategy for transmit descriptors is essentially the same as
for receive descriptors except that a different set of thresholds are used. Just as with
receives, the number of transmit descriptors held in hardware has been increased
(from 8 to 64), and the fetch and write-back algorithms modified.
When the hardware descriptor buffer is empty, a fetch will happen as soon as any
descriptors are made available (host writes to the tail pointer). When the hardware
descriptor buffer is nearly empty (TXDCTL.PTHRESH), a prefetch will be performed
whenever enough valid descriptors (TXDCTL.HTHRESH) are available in host memory
and no other DMA activity of greater priority is pending (descriptor fetches, descriptor
write-backs, or packet data transfers).
When the number of descriptors in host memory is greater than the available hardware
descriptor storage, the GbE may elect to perform a fetch which is not a multiple of
cache line size. The hardware performs this non-aligned fetch if doing so will result in
the next descriptor fetch being aligned on a cache line boundary. This allows the
descriptor fetch mechanism to be most efficient in the cases where it has fallen behind
software.
The GbE NEVER fetches descriptors beyond the descriptor TAIL pointer. This is different
from the 82542 design.
Transmit Descriptor Write-back
The descriptor write-back policy for transmit descriptors is similar to that for receive
descriptors with a few additional factors. First, since transmit descriptor write-backs
are optional (controlled by RS in the transmit descriptor), only descriptors which have
one (or both) of these bits set will start the accumulation of write-back descriptors.
Secondly, to preserve backward compatibility with the 82542, if the TXDCTL.WTHRESH
value is 0, the device will write back a single byte of the descriptor (TDESCR.STA) and
all other bytes of the descriptor will be left unchanged.
The benefit of delaying and then bursting transmit descriptor write-backs is small at
best. In this case, it is recommended the threshold be left at the default value (0) to
force immediate write-back of transmit descriptors and to preserve backward
compatibility.
Descriptors are written back in one of three cases:
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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