EP80579 Datasheet, PDF (61/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
16-75 Offset 62h: FSB_NERR - FSB Next Error Register ................................................ 469
16-76 Offset 64h: FSB_EMASK - FSB Error Mask Register ............................................. 470
16-77 offset 68h: FSB_SCICMD - FSB SCI Command Register ....................................... 471
16-78 Offset 6Ah: FSB_SMICMD - FSB SMI Command Register ...................................... 472
16-79 Offset 6Ch: FSB_SERRCMD - FSB SERR Command Register ................................. 473
16-80 Offset 6Eh: FSB_MCERRCMD - FSB MCERR Command Register ............................. 474
16-81 Offset 70h: BUF_FERR - Memory Buffer First Error Register ................................. 475
16-82 Offset 72h: BUF_NERR - Memory Buffer Next Error Register ................................. 475
16-83 Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register .............................. 476
16-84 Offset 78h: BUF_SCICMD - Memory Buffer SCI Command Register ....................... 477
16-85 Offset 7Ah: BUF_SMICMD - Memory Buffer SMI Command Register ...................... 478
16-86 Offset 7Ch: BUF_SERRCMD - Memory Buffer SERR Command Register .................. 479
16-87 Offset 7Eh: BUF_MCERRCMD - Memory Buffer MCERR Command Register .............. 480
16-88 Offset E4h: NSIERRINJCTL - NSI Error Injection Control Register .......................... 481
16-89 Offset E8h: BERRINJCTL - Buffer Error Injection Control Register .......................... 482
16-90 Offset 80h: DRAM_FERR - DRAM First Error Register ........................................... 483
16-91 Offset 82h: DRAM_NERR - DRAM Next Error Register .......................................... 484
16-92 Offset 84h: DRAM_EMASK - DRAM Error Mask Register ....................................... 486
16-93 Offset 88h: DRAM_SCICMD - DRAM SCI Command Register ................................. 487
16-94 Offset 8Ah: DRAM_SMICMD - DRAM SMI Command Register ................................ 488
16-95 Offset 8Ch: DRAM_SERRCMD - DRAM SERR Command Register ............................ 489
16-96 Offset 8Eh: DRAM_MCERRCMD - DRAM MCERR Command Register ....................... 490
16-97 Offset 98h: THRESH_SEC0 - Rank 0 SEC Error Threshold Register ......................... 491
16-98 Offset 9Ah: THRESH_SEC1 - Rank 1 SEC Error Threshold Register ........................ 491
16-99 Offset A0h: DRAM_SECF_ADD - DRAM First Single Bit Error Correct Address
Register ........................................................................................................ 492
16-100 Offset A4h: DRAM_DED_ADD - DRAM Double Bit Error Address Register ................ 492
16-101 Offset A8h: DRAM_SCRB_ADD - DRAM Scrub Error Address Register ..................... 493
16-102 Offset B0h: DRAM_SEC_R0 - DRAM Rank 0 SEC Error Counter Register ................. 494
16-103 Offset B2h: DRAM_DED_R0 - DRAM Rank 0 DED Error Counter Register ................ 494
16-104 Offset B4h: DRAM_SEC_R1 - DRAM Rank 1 SEC Error Counter Register ................. 494
16-105 Offset B6h: DRAM_DED_R1 - DRAM Rank 1 DED Error Counter Register ................ 495
16-106 Offset C2h: THRESH_DED - DED Error Threshold Register .................................... 495
16-107 Offset C4h: DRAM_SECF_SYNDROME - DRAM First Single Error Correct
Syndrome Register ......................................................................................... 496
16-108 Offset C6h: DRAM_SECN_SYNDROME - DRAM Next Single Error Correct
Syndrome Register .......................................................................................... 496
16-109 Offset C8h: DRAM_SECN_ADD - DRAM Next Single Bit Error Correct Address
Register ......................................................................................................... 497
16-110 Offset DCh: RANKTHREX - Rank Error Threshold Exceeded Register ...................... 498
16-111 Offset ECh: DERRINJCTL - DRAM Error Injection Control Register .......................... 499
16-112 Bus 0, Device 1, Function 0: Summary of EDMA PCI Configuration Registers ............ 501
16-113 Offset 00h: VID - Vendor Identification Register ................................................. 502
16-114 Offset 02h: DID - Device Identification Register ................................................. 502
16-115 Offset 04h: PCICMD - PCI Command Register .................................................... 503
16-116 Offset 06h: PCISTS - PCI Status Register .......................................................... 504
16-117 Offset 08h: RID - Revision Identification Register ............................................... 504
16-118 Offset 0Ah: SUBC - Sub-Class Code Register ...................................................... 505
16-119 Offset 0Bh: BCC - Base Class Code Register ....................................................... 505
16-120 Offset 0Eh: HDR - Header Type Register ............................................................ 505
16-121 Offset 10h: EDMALBAR - EDMA Low Base Address Register .................................. 506
16-122 Offset 2Ch: SVID - Subsystem Vendor Identification Register ................................ 506
16-123 Offset 2Eh: SID - Subsystem Identification Register ............................................. 507
16-124 Offset 34h: CAPPTR - Capabilities Pointer Register .............................................. 507
16-125 Offset 3Ch: INTRLINE - Interrupt Line Register ................................................... 507
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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