EP80579 Datasheet, PDF (1122/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.2.2.5 ICW4[0-1] - Initialization Command Word 4 Register
Table 30-10. ICW4[0-1] - Initialization Command Word 4 Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: 21h, 0A1h
Offset End: 21h, 0A1h
Size: 8 bit
Default: 01h
Power Well: Core
Bit Range
07 : 05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
SFNM
BUF
MSBM
AEOI
MM
Must be programmed to zero.
Special Fully Nested Mode:
0 = Disabled by writing a 0 to this bit.
1 = Special fully nested mode is programmed.
Buffered Mode:
This bit must be programmed to 0 which is non-buffered
mode.
Note: Writing ‘1’ will result in undefined behavior.
Master/Slave in Buffered Mode: Must be programmed
to 0.
Automatic End of Interrupt:
0 = This bit must normally be programmed to 0. This is
the normal end of interrupt.
1 = Automatic End of Interrupt (AEOI) mode is
programmed.
AEOI is discussed in Section 30.2.7.2.
Microprocessor Mode: Must be programmed to 1 to
indicate that the controller is operating in an Intel
Architecture-based system.
Note: Writing ‘0’ will result in undefined behavior.
Bit Reset
Value
0h
0h
0h
0h
0h
1
Bit Access
WO
WO
WO
WO
WO
30.2.2.6 OCW1[0-1] - Operational Control Word 1 (Interrupt Mask) Register
Table 30-11. OCW1[0-1]- Operational Control Word 1 (Interrupt Mask) Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: 021h, 0A1h
Offset End: 021h, 0A1h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
IRM
Interrupt Request Mask:
0 = The corresponding IRQ mask bit is cleared and
interrupt requests are again accepted by the
controller.
1 = The corresponding IRQ line is masked.
Masking IRQ2 on the master controller also masks the
interrupt requests from the slave controller.
Sticky
Bit Reset
Value
Bit Access
00h
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1122
August 2009
Order Number: 320066-003US