EP80579 Datasheet, PDF (1069/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-19. Offset 30h: SMI_EN - SMI Control and Enable Register (Sheet 2 of 3)
Description:
View: PCI
BAR: PMBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 30h
Offset End: 30h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
14
13
12
11
10 : 08
07
06
05
Bit Acronym
Bit Description
Sticky
PERIODIC_
EN
TCO_EN
Reserved
MCSMI_EN
Reserved
BIOS_RLS
SWSMI_
TMR_EN
APMC_EN
0 = Disable
1 = Enables an SMI# to be generated when the
PERIODIC_STS bit (PMBASE + 34h, bit 14) is set in
the SMI_STS register (PMBASE + 34h).
0 = Disables TCO logic generating an SMI#.
1 = Enables the TCO logic to generate SMI#.
See Chapter 32.0, “High Precision Event Timers” for
more details on TCO functions.
If the NMI2SMI_EN bit is set, then SMIs that are caused
by NMIs (i.e., rerouted) will not be gated by the TCO_EN
bit. Even if the TCO_EN bit is 0, the NMIs will still be
routed to cause the SMI#.
Note: This bit can not be written once the TCO_LOCK
bit (at offset 08h of TCO I/O Space) is set. This
prevents unauthorized software from disabling
the generation of TCO-based SMIs.
Reserved
0 = Disable.
1 = Enables IICH to trap accesses to the
microcontroller range (62h or 66h) and generate
an SMI#. Note that “trapped’ cycles will be claimed
by the IICH on PCI, but not forwarded to LPC.
Reserved
0 = This bit will always return 0 on reads. Writes of 0 to
this bit have no effect.
1 = Enables the generation of an SCI interrupt for ACPI
software when a one is written to this bit position
by BIOS software.
Note: GBL_STS being set will cause an SCI, even if
the SCI_EN bit is not set. Software must take
great care not to set the BIOS_RLS bit (which
causes GBL_STS to be set) if the SCI handler is
not in place.
0 = Disable. Clearing the SWSMI_TMR_EN bit before
the timer expires will reset the timer and the SMI#
will not be generated.
1 = Starts Software SMI# Timer. When the SWSMI
timer expires (the timeout period depends upon
the SWSMI_RATE_SEL bit setting),
SWSMI_TMR_STS is set and an SMI# is generated.
SWSMI_TMR_EN stays set until cleared by
software.
0 = Writes to the APM_CNT register will not cause an
SMI#.
1 = Enables writes to the APM_CNT register to cause an
SMI#
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RW
RW
RW
WO
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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