EP80579 Datasheet, PDF (25/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
24.2.1.4 Offset 06h: DS – Device Status Register ............................................ 898
24.2.1.5 Offset 08h: RID: Revision ID Register................................................ 899
24.2.1.6 Offset 09h: PI: Programming Interface Register .................................. 900
24.2.1.7 Offset 0Ah: SCC: Sub Class Code Register ......................................... 900
24.2.1.8 Offset 0Bh: BCC: Base Class Code Register ........................................ 900
24.2.1.9 Offset 20h: SM_BASE: SMB Base Address Register.............................. 901
24.2.1.10 Offset 2Ch: SVID: SVID Register ...................................................... 901
24.2.1.11 Offset 2Eh: SID: Subsystem Identification Register ............................. 902
24.2.1.12 Offset 3Ch: INTLN: Interrupt Line Register ......................................... 902
24.2.1.13 Offset 3Dh: NTPN: Interrupt Pin Register ........................................... 903
24.2.1.14 Offset 40h: HCFG: Host Configuration Register ................................... 903
24.2.1.15 Offset F8h: MANID: Manufacturer ID Register..................................... 904
24.3 SMBus Controller I/O-Mapped Configuration Register Details ................................. 905
24.3.1 SMBus Controller I/O-Mapped Configuration Register Descriptions ................ 906
24.3.1.1 Offset 00h: HSTS: Host Status Register ............................................. 906
24.3.1.2 Offset 02h: HCTL: Host Control Register ............................................ 908
24.3.1.3 Offset 03h: HCMD: Host Command Register ....................................... 912
24.3.1.4 Offset 04h: TSA: Transmit Slave Address Register............................... 912
24.3.1.5 Offset 05h: HD0: Data 0 Register ..................................................... 913
24.3.1.6 Offset 06h: HD1: Data 1 Register ..................................................... 913
24.3.1.7 Offset 07h: HBD: Host Block Data Register......................................... 914
24.3.1.8 Offset 08h: PEC: Packet Error Check Data Register.............................. 915
24.3.1.9 Offset 0Ch: AUXS: Auxiliary Status Register ....................................... 915
24.3.1.10 Offset 0Dh: AUXC: Auxiliary Control Register...................................... 916
24.3.1.11 Offset 0Eh: SMLC: SMLINK_PIN_CTL Register..................................... 916
24.3.1.12 Offset 0Fh: SMBC: SMBUS_PIN_CTL Register ..................................... 917
24.4 Host Controller................................................................................................ 918
24.4.1 Overview .............................................................................................. 918
24.4.2 Command Protocols................................................................................ 918
24.4.2.1 Quick Command ............................................................................. 918
24.4.2.2 Send Byte/Receive Byte................................................................... 919
24.4.2.3 Write Byte/Word............................................................................. 920
24.4.2.4 Read Byte/Word ............................................................................. 921
24.4.2.5 Process Call ................................................................................... 922
24.4.2.6 Block Read/Write ............................................................................ 923
24.4.2.7 I2C Read ...................................................................................... 925
24.4.2.8 Block Write-Block Read Process Call .................................................. 926
24.4.3 I2C Behavior ......................................................................................... 928
24.4.4 Heartbeat for Use with External LAN ......................................................... 928
24.5 Bus Arbitration................................................................................................ 928
24.6 Bus Timings.................................................................................................... 928
24.6.1 Clock Stretching..................................................................................... 928
24.6.2 Bus Time Out (CMI as SMB Master) ......................................................... 929
24.7 Interrupts/SMI#.............................................................................................. 929
24.8 CRC Generation and Checking ........................................................................... 930
24.8.1 Slave Interface I/O Space ....................................................................... 930
24.8.2 Register Details ..................................................................................... 931
24.8.2.1 Offset 09h: RSA: Receive Slave Address Register ................................ 931
24.8.2.2 Offset 0Ah: SD: Slave Data Register ................................................. 931
24.8.2.3 Offset 10h: SSTS: Slave Status Register ............................................ 932
24.8.2.4 Offset 11h: SCMD: Slave Command Register ...................................... 932
24.8.2.5 Offset 14h: NDA: Notify Device Address Register ................................ 933
24.8.2.6 Offset 16h: NDLB: Notify Data Low Byte Register ................................ 934
24.8.2.7 Offset 17h: NDHB: Notify Data High Byte Register .............................. 934
24.9 Slave Interface Behavioral Description ............................................................... 935
24.9.1 Format of Slave Write Cycle..................................................................... 935
24.9.2 Format of Read Command ....................................................................... 936
24.9.3 Format of the Host Notify Command ......................................................... 938
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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