EP80579 Datasheet, PDF (18/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
16.6.1.43 Offset D8h: DAR3 - Channel 3 Destination Address Register.................. 675
16.6.1.44 Offset DCh: DUAR3 - Channel 3 Destination Upper Address
Register ......................................................................................... 675
16.6.1.45 Offset E0h: NDAR3 - Channel 3 Next Descriptor Address Register .......... 675
16.6.1.46 Offset E4h: NDUAR3 - Channel 3 Next Descriptor Upper
Address Register ............................................................................. 676
16.6.1.47 Offset E8h: TCR3 - Channel 3 Transfer Count Register ......................... 676
16.6.1.48 Offset ECh: DCR3 - Channel 3 Descriptor Control Register .................... 677
16.6.1.49 Offset 100h: DCGC - EDMA Controller Global Command ....................... 677
16.6.1.50 Offset 104h: DCGS - EDMA Controller Global Status............................. 678
16.7 Memory Mapped I/O for NSI Registers ................................................................ 679
16.7.1 Register Details ...................................................................................... 680
16.7.1.1 Offset 00h: NSIVCECH - NSI Virtual Channel Enhanced Capability Header
Register ......................................................................................... 680
16.7.1.2 Offset 04h: NSIPVCCAP1 - NSI Port VC Capability Register 1................. 680
16.7.1.3 Offset 08h: NSIPVCCAP2 - Port VC Capability Register 2....................... 681
16.7.1.4 Offset 0Ch: NSIPVCCTL - NSI Port VC Control Register ......................... 682
16.7.1.5 Offset 10h: NSIVC0RCAP - NSI VC0 Resource Capability Register .......... 682
16.7.1.6 Offset 14h: NSIVC0RCTL - NSI VC0 Resource Control Register .............. 683
16.7.1.7 Offset 1Ah: NSIVC0RSTS - NSI VC0 Resource Status Register ............... 684
16.7.1.8 Offset 80h: NSIRCILCECH - NSI Root Complex Internal Link Control Enhanced
Capability Header Register................................................................ 684
16.7.1.9 Offset 84h: NSILCAP - NSI Link Capabilities Register............................ 685
Integrated I/O Controller Hub, Volume 3 of 6 ............................. 687
17.0 Bridging and Configuration .................................................................................... 689
17.1 Root Complex Memory-Mapped Configuration Register Details ............................... 689
17.1.1 VC Configuration Registers....................................................................... 691
17.1.1.1
17.1.1.2
17.1.1.3
17.1.1.4
17.1.1.5
17.1.1.6
17.1.1.7
17.1.1.8
Offset 0000h: VCH - Virtual Channel Capability Header Register ............ 691
Offset 0004h: VCAP1 - Virtual Channel Capability 1 Register ................. 691
Offset 0008h: VCAP2 - Virtual Channel Capability 2 Register ................. 692
Offset 000Ch: PVC - Port Virtual Channel Control Register .................... 692
Offset 000Eh: PVS - Port Virtual Channel Status Register...................... 693
Offset 0010h: V0CAP - Virtual Channel 0 Resource Capability
Register ......................................................................................... 693
Offset 0014h: V0CTL - Virtual Channel 0 Resource Control Register ....... 694
Offset 001Ah: V0STS - Virtual Channel 0 Resource Status Register ........ 695
17.1.2 Root Complex Topology Capability Structure Registers................................. 696
17.1.2.1
17.1.2.2
17.1.2.3
17.1.2.4
Offset 0100h: RCTCL- - Root Complex Topology Capabilities List Register ....
696
Offset 0104h: ES - Element Self Description Register ........................... 696
Offset 0110h: ULD - Upstream Link Description Register....................... 697
Offset 0118h: ULBA - Upstream Link Base Address Register .................. 697
17.1.3 Internal Link Configuration Registers ......................................................... 698
17.1.3.1
17.1.3.2
17.1.3.3
17.1.3.4
Offset 01A0h: ILCL - Internal Link Capabilities List Register .................. 698
Offset 01A4h: LCAP - Link Capabilities Register ................................... 698
Offset 01A8h: LCTL - Link Control Register ......................................... 699
Offset 01AAh: LSTS - Link Status Register .......................................... 700
17.1.4 TCO Configuration .................................................................................. 700
17.1.4.1 Offset 3000h: TCTL - TCO Control Register ......................................... 700
17.1.5 Interrupt Configuration Registers .............................................................. 701
17.1.5.1
17.1.5.2
17.1.5.3
17.1.5.4
17.1.5.5
Offset 3100h: D31IP - Device 31 Interrupt Pin Register ........................ 701
Offset 3108h: D29IP - Device 29 Interrupt Pin Register ........................ 702
Offset 3140h: D31IR - Device 31 Interrupt Route Register .................... 702
Offset 3144h: D29IR - Device 29 Interrupt Route Register .................... 703
Offset 31FFh: OIC - Other Interrupt Control Register ........................... 704
17.1.6 General Configuration Registers................................................................ 704
Intel^® EP80579 Integrated Processor Product Line Datasheet
18
August 2009
Order Number: 320066-003US