EP80579 Datasheet, PDF (640/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.5.1.60 Offset 1F8h: MB_ERR_DATA33 - Memory Test Error Data 3
Stores the fourth 32 bits of the 4th 144 bit failure data
Table 16-285.Offset 1F8h: MB_ERR_DATA33 - Memory Test Error Data 3
Description: MB_ERR_DATA33
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 1F8h
Offset End: 1FBh
Size: 32 bit
Default: 00h
Power Well: Core
Bit Range
31 :00
Bit Acronym
Bit Description
DATA
Late failure data [63:32]
Sticky
Y
Bit Reset
Value
00000000h
Bit Access
RW
16.5.1.61 Offset 1FCh: MB_ERR_DATA34 - Memory Test Error Data 3
Stores the last 16 bits of the 4th 144 bit failure data.
Table 16-286.Offset 1FCh: MB_ERR_DATA34 - Memory Test Error Data 3
Description: MB_ERR_DATA34
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 1FCh
Offset End: 1FDh
Size: 16 bit
Default: 00h
Power Well: Core
Bit Range
15 :00
Bit Acronym
Bit Description
DATA
Late failure data [71:64] & Early failure data [71:64]
Sticky
Y
Bit Reset
Value
0000h
Bit Access
RW
16.5.1.62 Offset 260h: DDRIOMC0 - DDR IO Mode Control Register 0
This register controls functionality of the DDRIO.
This CSR is in the memory-mapped IO region of Bus 0, Device 0, Function 0 of the
memory controller. The SMRBASE register described in Section 16.1.1.9, “Offset 14h:
SMRBASE - System Memory RCOMP Base Address Register” on page 395, provides the
base address for these registers. The offsets listed for the following registers are
relative to this base address.
The value for BAR for all registers in this section is BAR14h.
One function of DDRIOMC0 is to control the Voltage Crossing (VOX) analog control loop
used to minimize any mismatch between the clock to output (Tco) on a low-to-high or
high-to-low transition.
Intel^® EP80579 Integrated Processor Product Line Datasheet
640
August 2009
Order Number: 320066-003US