EP80579 Datasheet, PDF (427/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-45. Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 4 of 7)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 78h
Offset End: 7Bh
Size: 32 bit
Default: 242AD280h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
This bit controls the number of DRAM clocks to enforce as
the RAS cycle time.
Bit Reset
Value
Bit Access
16 :12
Trc
Encoding
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
Others
Number of CMDCLK
delays
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Reserved
N
01101b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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