EP80579 Datasheet, PDF (1226/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
34.2.2.23 Offset 28h: PMBASU – Prefetchable Memory Base Upper Register
Table 34-25. Offset 28h: PMBASU: Memory Limit Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 28h
Offset End: 28h
Size: 8bit
Default: Fh
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 04
03 : 00
RSV
BUA
These bits are reserved
Base Upper Address
Sticky
Bit Reset
Value
0h
Fh
Bit Access
RO
RW
Note:
Prefetchable memory space is not used by AIOC. BIOS and enumeration software must
be checked to make sure these default values are never modified to enable
prefetchable memory space. Writing to this register can result in undefined behavior.
34.2.2.24 Offset 2Ch: PMLMTU – Prefetchable Memory Limit Upper Register
Note:
Prefetchable memory space is not used by AIOC. BIOS and enumeration software must
be checked to make sure these default values are never modified to enable
prefetchable memory space. Writing to this register can result in undefined behavior.
Table 34-26. Offset 2Ch: PMLMTU: Prefetchable Memory Limit Upper Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 2Ch
Offset End: 2Ch
Size: 8 bit
Default: 0
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 04
03 : 00
RSV
LUA
Reserved
Limit Upper Address
Sticky
Bit Reset
Value
0h
0h
Bit Access
RO
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1226
August 2009
Order Number: 320066-003US