EP80579 Datasheet, PDF (936/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 24-55. Slave Write Registers
Register
0
1–3
4
5
6–7
8
9 – FFh
Function:
Command Register. See Table 24-56 for legal values written to this register.
Reserved
Data Message Byte 0
Data Message Byte 1
Reserved
Reserved
Reserved
Note:
The external microcontroller is responsible to make sure that it does not update the contents of the data
byte registers until they have been read by the system processor. The CMI overwrites the old value with
any new value received. A race condition is possible where the new value is being written to the register
just at the time it is being read. The CMI does not attempt to cover this race condition (i.e.,
unpredictable results in this case).
Table 24-56. Command Types
Command Type
Description
0
1
2
3
4
5
6
7
8
9 – FFh
Reserved
WAKE/SMI#: Wake system if it is not already awake. If system is already awake, then an
SMI# is generated.
Unconditional Powerdown: This command should set the PWRBTNOR_STS bit, and
have the same effect as the power button override occurring.
HARD RESET Without Power Cycling SYSTEM: The causes a soft reset of the system
(does not include cycling of the power supply). This is equivalent to a write to the CF9h
register with bits 02:01 set to 1, but bit 03 set to 0.
HARD RESET SYSTEM: The causes a hard reset of the system (including cycling of the
power supply). This is equivalent to a write to the CF9h register with bits 03:01 set to 1.
Disable the TCO Messages. This command disables the IICH from sending Heartbeat
and Event messages. Once this command has been done, there is no method to reenable
the Heartbeat and Event messages, until CF9 RESET or RSMRST# goes low and then high.
WD RELOAD: Reload watchdog timer.
Reserved
SMLINK_SLAVE_SMI: When the CMI detects this command type while in the S0 state, it
will set the SMLINK_SLAVE_SMI_STS bit. This command should only be used if the system
is in an S0 state. If the message is received during S3 or S5 states, it is acknowledged by
the CMI but the SMLINK_SLAVE_SMI_STS bit is not set.
Note: It is possible that the system transitions out of the S0 state at the same time that
the SMLINK_SLAVE_SMI command is received. In this case, the
SMLINK_SLAVE_SMI_STS bit may get set but not serviced before the system goes
to sleep. Once the system returns to S0, the SMI associated with this bit would
then be generated. Software must be able to handle this scenario.
Reserved
24.9.2
Format of Read Command
The external master performs byte read commands to the SMBus Slave Interface. The
Command field (bits 11-18) indicate which register is being accessed. The Data field
(bits 30-37) indicate the value that should be read from that register. Table 24-57
shows the read cycle format. Table 24-58 shows the register mapping for the data
byte.
Intel^® EP80579 Integrated Processor Product Line Datasheet
936
August 2009
Order Number: 320066-003US