EP80579 Datasheet, PDF (1613/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 40-4. Motorola^* SPI Frame Formats for SPO and SPH Programming
SSP_SC
LK
SPO=0
...
SSP_SC
LK
SPO=1
...
SSP_SF
RM
...
SSP_TX
D4
Bit<N> Bit<N..> ... Bit<1> Bit<0>
SSP_RX
D4
SSP_SC
LK
SPO=0
SSP_SC
LK
SPO=1
SSP_SF
RM
SSP_TX
D4
Bit<N>
MSB
Bit<N..> ... Bit<1> Bit<0>
4 to 16 Bits
LSB
SPH = 0
...
...
...
Bit<N> Bit<N..> ... Bit<1> Bit<0>
40.4.2.7
SSP_RX
D4
Bit<N>
MSB
Bit<N..> ... Bit<1> Bit<0>
4 to 16 Bits
LSB
SPH = 1
National Microwire* Data Size (MWDS)
This bit sets the size of data in the Microwire format. If ‘1’, a 16 bits data size is chosen
for the Microwire format, otherwise, an 8-bit data size.
40.4.2.8
Transmit FIFO Interrupt Threshold (TFT)
This 4-bit value sets the level at or below which the FIFO controller triggers a service
interrupt.
40.4.2.9
Receive FIFO Interrupt Threshold (RFT)
This 4-bit value sets the level at or above which the FIFO controller triggers a service
interrupt.
40.4.2.10 Enable FIFO Write/Read Function (EFWR)
This bit enables a special functional mode for the SSP. When EFWR = 0, the SSP
operates in the normal mode described in this document. When EFWR = 1, the SSP
enters a mode in which whenever the CPU reads or writes to the SSP Data register, it
actually reads and writes exclusively to either the Transmit FIFO or the Receive FIFO
depending on the programmed state of the Select FIFO for EFWR (STRF) bit. In this
special mode, data will not be transmitted on the TXD pin and data input on the RXD
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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