EP80579 Datasheet, PDF (1021/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.4
EHC Initialization
The following describes the expected EHC initialization sequence in chronological order,
beginning with a complete power cycle in which the suspend well and core well have
been off.
26.4.1
Power On
The suspend well is a “deeper” power plane than the core well, which means that the
suspend well is always functional when the core well is functional but the core well may
not be functional when the suspend well is. Therefore, the suspend well reset pin
(RSMRST#) deasserts before the core well reset pin (PWROK) rises.
1. The suspend well reset deasserts, leaving all registers and logic in the suspend well
in the default state. However, it is not possible to read any registers until after the
core well reset deasserts.
2. The core well reset deasserts, leaving all registers and logic in the core well in the
default state. The EHC configuration space is accessible at this point. The core well
reset can (and typically does) occur without the suspend well reset asserting. This
means that all of the Configure Flag and Port Status and Control bits (and any other
suspend-well logic) may be in any valid state at this time.
26.4.2
Driver Initialization
See Chapter 4 of the EHCI Specification, Rev. 1.0.
26.4.3 EHC Resets
In addition to the standard hardware resets, portions of the EHC are reset by the
HCRESET bit and the transition from the D3hot device power management state to the
D0 state. The effect of each of these resets are:
Table 26-49. HCRESET Bit Summary
Reset
Does Reset
HCRESET bit set
Memory space registers
except Structural
Parameters (which is
written by BIOS)
Software writes the
Device Power State from
D3hot (11b) to D0 (00b)
Core-well registers
(except BIOS-
programmed registers)
Does Not Reset
Configuration
Registers
Suspend-well
registers; BIOS-
programmed Core-well
Registers
Comments
The HCRESET must only
affect registers that the EHCI
driver controls. PCI
Configuration space and
BIOS-programmed
parameters must not be
reset.
The D3-to-D0 transition must
not cause wake information
(suspend well) to be lost. It
also must not clear BIOS-
programmed registers
because BIOS may not be
invoked following the D3-to-
D0 transition.
If the detailed register descriptions give exceptions to these rules, those exceptions
override these rules. This summary is provided to help explain the reasons for the reset
policies.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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