EP80579 Datasheet, PDF (1492/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-67. TCTL: Transmit Control Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0400h
Offset End: 0403h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0400h
Offset End: 0403h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0400h
Offset End: 0403h
Size: 32 bits
Default: 00000008h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
11 : 04
03
02
01
00
Bit Acronym
Bit Description
Sticky
CT
PSP
Rsvd
EN
Rsvd
Collision Threshold. Software may choose to abort
packet transmission in less than the Ethernet mandated 16
collisions. This field determines the number of attempts at
retransmission prior to giving up on the packet (not
including the first transmission attempt). The Ethernet
back-off algorithm is implemented and clamps to the
maximum number of slot-times after 10 retries. This field
only has meaning when in half-duplex operation.
Note: While this field can be varied, it should be set to a
value of 15 in order to comply with the IEEE
specification requiring a total of 16 attempts.
Pad Short Packets to 64B with valid data characters, NOT
padding symbols.
0 = Do not pad short packets
1 = Pad short packets
Note: This is not the same as the mini-mum collision
distance.
Reserved.
Enable.
0 = Writing this bit to 0 will stop transmission after any in
progress packets are sent. Data remains in the
transmit FIFO until the device is re-enabled. Software
should combine this with reset if the packets in the
FIFO should be flushed.
1 = The transmitter is enabled.
Reserved.
Bit Reset
Value
0h
1h
0h
0h
0h
Bit Access
RW
RW
RV
RW
RV
Intel^® EP80579 Integrated Processor Product Line Datasheet
1492
August 2009
Order Number: 320066-003US