EP80579 Datasheet, PDF (1253/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.6.1.20 Offset E0h: PMCS – Power Management Control and Status Register
For an overview of the power management capability of the EP80579 integrated
processorAIOC devices, see Section 35.5, “Power Management of AIOC Devices”.
Table 35-25. Offset E0h: PMCS: Power Management Control and Status Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:0:0
Offset Start: E0h
Offset End: E1h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:1:0
Offset Start: E0h
Offset End: E1h
View: PCI 3
BAR: Configuration
Bus:Device:Function: M:2:0
Offset Start: E0h
Offset End: E1h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15
14 : 13
12 : 09
08
07 : 04
03
02
01 : 00
Bit Acronym
Bit Description
Sticky
PME Status (sticky) This bit is sticky for device 0 which is
on suspend well, but not for the other 2 which aren’t on a
power well.
0 = Writing a 0 has no effect.
1 = Set when GBE would normally assert the PME# signal
PME_STATUS independent of the state of the PME_En bit.
Y
Note: Writing a 1 to this bit will clear it and cause the
internal PME to de-assert (if enabled). This bit must be
explicitly cleared by the operating
Note: On a write this register will be updated after a 100ns
delay.
Data Scale
DATA_SCALE _{Hardwired to “00” because it does not support the}
associated Data register.
DATA_SEL
Data Select
Hardwired to “0000” because it does not support the
associated Data register.
PME Enable (sticky) This bit is sticky for device 0 which is
on suspend well, but not for the other 2 which aren’t on a
power well.
PME_EN
A ‘1’ enables GbE to generate an internal PME signal when
PME_Status is ‘1’. This bit must be explicitly cleared by the
Y
operating system each time it is initially loaded.
Note: On a write this register will be updated after a 100ns
delay.
Reserved Reserved
NSR
No Soft Reset
Reserved Reserved
Power State
This 2-bit field is used both to determine the current power
state of GbE function and to set a new power state. The
definition of the field values are:
PS
00b – D0 state
11b – D3_HOT state
If software attempts to write a value of 10b or 01b in to
this field, the write operation must complete normally;
however, the data is discarded and no state change occurs.
Bit Reset
Value
0h
00b
0000b
0h
0000b
0h
0h
00b
Bit Access
RWC
RO
RO
RW
RO
RO
RO
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1253