EP80579 Datasheet, PDF (1119/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.2.2.1
ICW1[0-1] - Initialization Command Word 1 Register
A write to Initialization Command Word 1 starts the interrupt controller initialization
sequence, during which the following occurs:
1. The Interrupt Mask register is cleared.
2. IRQ7 input is assigned priority 7.
3. The slave mode address is set to 7.
4. Special Mask Mode is cleared and Status Read is set to IRR.
Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to
complete the initialization sequence.
Table 30-6. ICW1[0-1] - Initialization Command Word 1 Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: 020h, 0A0h
Offset End: 020h, 0A0h
Size: 8 bit
Default: 0001X0XXb
Power Well: Core
Bit Range
07 : 05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
Reserved
LTIM
Reserved
SNGL
IC4
Reserved. Must be programmed to zero.
Reserved. Must be programmed to one.
Edge/Level Bank Select: Disabled. Replaced by the
edge/level triggered control registers (ELCR, D31, F0,
4D0h and D31, F0, 4D1h).
Reserved. Must be programmed to zero.
Single or Cascade: This bit must be programmed to a 0
to indicate that two controllers are operating in cascade
mode.
ICW4 Write Required: This bit must be programmed to
a 1 to indicate that ICW4 needs to be programmed.
Bit Reset
Value
000h
1
X
0h
X
X
Bit Access
WO
WO
WO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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