EP80579 Datasheet, PDF (870/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.3.4.5 Offset 130h: PxSERR[0-1] – Port [0-1] Serial ATA Error Register
Table 23-68. Offset 130h: PxSERR[0-1] – Port [0-1] Serial ATA Error Register (Sheet 1 of 2)
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 130h, 1B0h
Offset End: 133h, 1B3h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Diagnostics (DIAG) - Contains diagnostic error
information for use by diagnostic software in validating
correct operation or isolating failure modes:
Sticky
Bit Reset
Value
Bit Access
31 : 16
DIAG
Bits
Description
31:2
7
Reserved
Exchanged (X): When set to ‘1’ this bit indicates a
26 COMINIT signal was received. This bit is reflected in
the interrupt register PxIS. PCS.
Unrecognized FIS Type (F): Indicates that one or
25
more FISs were received by the Transport layer with
good CRC, but had a type field that was not
recognized/known.
Transport state transition error (T): Indicates that an
24
error has occurred in the transition from one state to
another within the Transport layer since the last time
this bit was cleared.
Link Sequence Error (S): Indicates that one or more
Link state machine error conditions was encountered.
23 The Link Layer state machine defines the conditions
under which the link layer detects an erroneous
transition.
Handshake Error (H): Indicates that one or more
R_ERR handshake response was received in
response to frame transmission. Such errors may be
22 the result of a CRC error detected by the recipient, a
disparity or 8b/10b decoding error, or other error
condition leading to a negative handshake on a
transmitted frame.
21
CRC Error (C): Indicates that one or more CRC errors
occurred with the Link Layer.
20 Disparity Error (D): This field is not used by AHCI.
19
10B to 8B Decode Error (B): Indicates that one or
more 10B to 8B decoding errors occurred.
18
Comm Wake (W): Indicates that a Comm Wake signal
was detected by the Phy.
17
Phy Internal Error (I): Indicates that the Phy detected
some internal error.
PhyRdy Change (N): When set to 1 this bit indicates
that the internal PhyRdy signal changed state since
the last time this bit was cleared. In the ICH6, this bit
16
will be set when PhyRdy changes from a 0 -> 1 or a 1
-> 0. The state of this bit is then reflected in the
PxIS.PRCS interrupt status bit and an interrupt will be
generated if enabled. Software clears this bit by
writing a 1 to it.
0000h
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
870
August 2009
Order Number: 320066-003US