EP80579 Datasheet, PDF (929/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.6.2
The CMI monitors the SM Bus clock line after it releases the bus to determine whether
to enable the counter for the high time of the clock. While the bus is still low, the high
time counter must not be enabled. Similarly, the low period of the clock can be
stretched by an SM Bus master if it is not ready to send or receive data.
Bus Time Out (CMI as SMB Master)
If there is an error in the transaction, such that an SMBus device does not signal an
acknowledge, or holds the clock lower than the allowed time-out time, the transaction
will time out. The CMI discards the cycle, and set the DEV_ERR bit. The time out
minimum is 25 ms. The time-out counter inside the CMI starts when the first bit of data
is transferred by the CMI. The time-out minimum is 25 ms (800 RTC clocks).
The 25 ms timeout counter does not count under the following conditions:
1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, bit 7) is set, and
2. The SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is not set (this indicates that
the system has not locked up).
24.7
Interrupts/SMI#
The CMI SM Bus controller uses PIRQB# as its interrupt pin. However, the system can
alternatively be set up to generate SMI# instead of an interrupt, by setting the
SMBUS_SMI_EN bit (Device 31, Function 0, Offset 40h, bit 1).
The following tables specify how the various enable bits in the SMBus function control
the generation of the interrupt, Host and Slave SMI, and Wake internal signals. The
rows in the tables are additive, which means that if more than one row is true for a
particular scenario then the results for all of the activated rows occurs.
Table 24-43. Summary of Enables for SMBALERT#
Event
SMBALERT# asserted
low (always reported
in SMBALERT_STS-
Host Status Register,
bit 5)
INTREN (Host
Control I/O
Register, Offset
02h, Bit 0)
X
X
1
SMB_SMI_EN (Host
Configuration Register,
D31, F3, Offset 40h,
Bit 1)
SMBALERT_DIS (Slave
Command I/O
Register, Offset 11h,
Bit 2)
Result
X
X
Wake generated
Slave SMI#
1
0
generated
(SMBUS_SMI_STS)
0
0
Interrupt generated
Table 24-44. Summary of Enables for SMBus Slave Write, and SMBus Host Events
Event
Slave Write to Wake/SMI#
command
Slave Write to
SMLINK_SLAVE_SMI
command
Any combination of Host
Status Register [04:01]
asserted
INTREN (Host Control I/O
Register, Offset 02h, Bit 0)
X
X
0
1
1
SMB_SMI_EN (Host
Configuration Register,
D31, F3,
Offset 40h, Bit 1)
X
X
X
0
1
Result
Wake generated when asleep
Slave SMI# generated when
awake (SMBUS_SMI_STS)
Slave SMI# generated when
in the S0 state
(SMBUS_SMI_STS)
None
Interrupt generated
Host SMI# generated
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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