EP80579 Datasheet, PDF (777/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
20.2.1.14 Offset 0Fh: DMA_WAM - DMA Write All Mask Register
Table 20-17. Offset 0Fh: DMA_WAM - DMA Write All Mask Register
Description:
View: IA F 1^a Base Address: 0000h (IO)
Offset Start: 0Fh
Offset End: 0Fh
View: IA F 1 Base Address: 0000h (IO)
Offset Start: 1Fh
Offset End: 1Fh
View: IA F 2^b Base Address: 0000h (IO)
Offset Start: DEh
Offset End: DEh
View: IA F 2 Base Address: 0000h (IO)
Offset Start: DFh
Offset End: DFh
Size: 8 bit
Default: 00001111b
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
07 : 04
03 : 00
Reserved
CMSKB
Reserved. Must be 0.
Channel Mask Bits: Setting the bit(s) to a 1 disables the
corresponding DREQ(s). Setting the bit(s) to a 0 enables
the corresponding DREQ(s). Bits [03:00] are set to 1 upon
part reset or Master Clear. When read, bits [03:00]
indicate the DMA channel [03:00] ([07:04]) mask status.
0 Channel 0 (4)
1 Channel 1 (5)
2 Channel 2 (6)
3 Channel 3 (7)
This register permits all four channels to be
simultaneously enabled/disabled instead of enabling/
disabling each channel individually, as is the case with the
Mask Register - Write Single Mask Bit. This register also
has a read path to allow the status of the channel mask
bits to be read. A channel's mask bit is automatically set
to 1 when the Current Byte/Word Count Register reaches
terminal count (unless the channel is in auto-initialization
mode).
Disabling channel 4 also disables channels 0–3 due to the
cascade of channels 0–3 through channel 4.
a. View 1 describes the control registers for Channels 0-3.
b. View 2 describes the control registers for Channels 4-7.
Bit Reset
Value
0h
1111b
Bit Access
RO
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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