EP80579 Datasheet, PDF (917/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 24-29. Offset 0Eh: SMLC: SMLINK_PIN_CTL Register (Sheet 2 of 2)
Description:
View: PCI
Size: 8 bit
BAR: SM_BASE (IO)
Default: 07h
Bus:Device:Function: 0:31:3
Offset Start: 0Eh
Offset End: 0Eh
Power Well: Resume^a
Bit Range Bit Acronym
Bit Description
Sticky
This read-only bit has a default value that is dependent
on an external signal level. This pin returns the value on
00
SMLINK0_CUR_ ^{the SMLINK[0] pin.}
STS
0 = Low
1 = High
This allows software to read the current state of the pin.
a. Reset by CF9 RESET or RSMRST#
Bit Reset
Value
0h
Bit Access
RO
24.3.1.12 Offset 0Fh: SMBC: SMBUS_PIN_CTL Register
This register is in the resume well and is reset by CF9 RESET or RSMRST#.
Table 24-30. Offset 0Fh: SMBC: SMBUS_PIN_CTL Register
Description:
View: PCI
Size: 8 bit
BAR: SM_BASE (IO)
Default: 07h
Bus:Device:Function: 0:31:3
Offset Start: 0Fh
Offset End: 0Fh
Power Well: Resume^a
Bit Range Bit Acronym
Bit Description
Sticky
07 : 03
02
01
00
Reserved Reserved
SMBCLK_CTL
This bit has a default of 1.
0 = Drives the SMBCLK pin low, independent of what
the other SMB logic would otherwise indicate for
the SMBCLK pin.
1 = The SMBCLK pin is Not overdriven low. The other
SMBus logic controls the state of the pin.
SMBDATA_
CUR_STS
This bit has a default value that is dependent on an
external signal level.
This pin returns the value on the SMBDATA pin. This
allows software to read the current state of the pin.
0 = Low
1 = High
SMBCLK_
CUR_STS
This bit has a default value that is dependent on an
external signal level. This pin returns the value on the
SMBCLK pin. This allows software to read the current
state of the pin.
0 = Low
1 = High
a. Reset by CF9 RESET or RSMRST#
Bit Reset
Value
00h
1b
1b
1b
Bit Access
RO
RW
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
917