EP80579 Datasheet, PDF (1015/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.3.2.7
Offset 38h: ASYNCLISTADDR - Current Asynchronous List Address
Register
This 32-bit register contains the address of the next asynchronous queue head to be
executed. Since the host controller operates in 64-bit mode (as indicated by a one in
64-bit Addressing Capability field in the HCCPARAMS register), then the most
significant 32 bits of every control data structure address comes from the
CTRLDSSEGMENT register. Bits [4:0] of this register cannot be modified by system
software and will always return zeros when read. The memory structure referenced by
this physical memory pointer is assumed to be 32-byte aligned.
Table 26-46. Offset 38h: ASYNCLISTADDR - Current Asynchronous List Address Register
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 38h
Offset End: 3Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :05
04 :00
Bit Acronym
Bit Description
Sticky
LPL
Reserved
Link Pointer Low: These bits correspond to memory
address signals [31:5], respectively. This field may only
reference a Queue Head (QH).
Reserved.
Bit Reset
Value
0h
0h
Bit Access
RW
26.3.2.8
Offset 60h: CONFIGFLAG - Configure Flag Register
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset. This 32-bit
register contains the address of the next asynchronous queue head to be executed.
Since the host controller operates in 64-bit mode (as indicated by a 1 in 64-bit
Addressing Capability field in the HCCPARAMS register), then the most significant 32
bits of every control data structure address comes from the CTRLDSSEGMENT register
(offset 08h). Bits [4:0] of this register cannot be modified by system software and will
always return 0’s when read. The memory structure referenced by this physical
memory pointer is assumed to be 32-byte aligned.
Table 26-47. Offset 60h: CONFIGFLAG - Configure Flag Register
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 60h
Offset End: 63h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :01
00
Bit Acronym
Bit Description
Sticky
Reserved
CF
Reserved. Reads from this field will always return 0.
Configure Flag: Host software sets this bit as the last
action in its process of configuring the Host Controller.
This bit controls the default port-routing control logic. Bit
values and side effects are listed below. See section 4 of
the EHCI Specification for operation details.
0 = Port routing control logic default-routes each port to
the classic host controllers.
1 = Port routing control logic default-routes all ports to
this host controller.
Bit Reset
Value
0h
0h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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